Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been placed in the file of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 21 and 30-33 are rejected under 35 U.S.C. 103 as being unpatentable over Moon et al. (US Pub # 2021/0225426).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Moon et al. teach a memory device comprising: an alignment data strobing signal generation circuit configured to receive a read identification signal, read channel signal, and internal clock signal (see Fig. 1-2, 11-16, 18 and paragraph 0006-0009, 0034-0043, 0054-0056, 0122-0133, 0137-0154, 0158-0175, Command CMD includes read identification signal, SID is read channel signal, CLK is clock signal) and to generate an alignment data strobing signal from the internal clock signal when a read operation on a specific pseudo channel of a specific rank is performed based on the read identification signal and the read channel signal (see Fig. 1-2, 11-16, 18 and paragraph 0006-0009, 0034-0043, 0054-0056, 0122-0133, 0137-0154, 0158-0175, unit 412-iCMD is alignment data strobing signal); and a core pipe configured to receive the alignment data strobing signal and to output core data output from the specific pseudo channel, based on the alignment data strobing signal (see Fig. 1-2, 11-16, 18 and paragraph 0006-0009, 0034-0043, 0054-0056, 0122-0133, 0137-0154, 0158-0175, based on iCMD to core die, core data output DATA).
Even though Moon et al. teach core die 420, 430 and core data “DATA” but silent exclusively about core pipe. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Moon et al. where core die receive the iCMD signal through signal line 403, 402 which would be called core pipe in order to improve reliability of read data strobe signal (see paragraph 0199).
Regarding claim 2, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Moon et al. further teach, wherein the read identification signal indicates the specific rank (see Fig. 1-2, 11-16, 18 and paragraph 0006-0009, 0034-0043, 0054-0056, 0122-0133).
Regarding claim 3, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Moon et al. further teach, wherein the read channel signal indicates the specific pseudo channel (see Fig. 1-2, 11-16, 18 and paragraph 0006-0009, 0034-0043, 0054-0056).
Regarding claim 4, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Moon et al. further teach, further comprising a base die configured to receive an external clock signal and an external command and to generate the read identification signal and the read channel signal, based on the external clock signal and the external command (see Fig. 1-2, 11-16, 18 and paragraph 0006-0009, 0034-0043, 0054-0056, 0122-0133, 0137).
Regarding claim 5, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 4 on which this claim depends.
Moon et al. further teach, wherein the base die includes: a command decoder configured to decode the external command in synchronization with the external clock signal received from a memory controller to generate a read command, a channel signal, and an identification signal; and a read control circuit configured to generate the read identification signal and the read channel signal, based on the read command, the channel signal, and the identification signal (see Fig. 1-2, 11-16, 18 and paragraph 0006-0009, 0034-0043, 0054-0056, 0122-0133, 0137-0154, 0158-0165).
Regarding claim 6, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 5 on which this claim depends.
Moon et al. further teach, wherein the base die further includes an internal clock signal generation circuit configured to divide the external clock signal to generate the internal clock signal (see Fig. 1-2, 11-16, 18 and paragraph 0006-0009, 0034-0043, 0054-0056, 0122-0133).
Regarding claim 7, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 4 on which this claim depends.
Moon et al. further teach, further comprising a plurality of core dies stacked over the base die, wherein each of the plurality of core dies includes a plurality of channels, and wherein each of the plurality of channels includes a plurality of pseudo channels (see Fig. 1-2, 11-16, 18 and paragraph 0006-0009, 0034-0043, 0054-0056, 0122-0130).
Regarding claim 8, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 7 on which this claim depends.
Moon et al. further teach, wherein the channels included in the core dies form at least one rank for setting a bandwidth (see Fig. 1-2, 11-16, 18 and paragraph 0006-0009, 0034-0043, 0054-0056).
Regarding claim 9, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 7 on which this claim depends.
Moon et al. further teach, wherein each of the plurality of core dies includes the alignment data strobing signal generation circuit configured to receive the read identification signal and the read channel signal from the base die to generate the alignment data strobing signal (see Fig. 1-2, 11-16, 18 and paragraph 0006-0009, 0034-0043, 0054-0056, 0122-0133, 0137-0144).
Regarding claim 10, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 7 on which this claim depends.
Moon et al. further teach, wherein each of the plurality of core dies includes the core pipe configured to output the core data to the base die (see Fig. 1-2, 11-16, 18 and paragraph 0006-0009, 0034-0043, 0054-0056, 0122-0131).
Regarding claim 21, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Moon et al. further teach, further comprising: a control through via array configured to transmit the read identification signal and the read channel signal received from a base die to the alignment data strobing signal generation circuit; and a data through via array configured to transmit the core data output from the core pipe to the base die (see Fig. 1-2, 11-16, 18 and paragraph 0006-0009, 0034-0043, 0054-0056, 0122-0133, 0137-0154).
Regarding independent claim 30, Moon et al. teach a memory device comprising: a plurality of core dies stacked over a base die, wherein each of the plurality of core dies comprises: an alignment data strobing signal generation circuit configured to receive an internal clock signal, a read identification signal, and a read channel signal from the base die to generate an alignment data strobing signa (see Fig. 1-2, 11-16, 18 and paragraph 0006-0009, 0034-0043, 0054-0056, 0122-0133, 0137-0154, 0158-0175, Command CMD includes read identification signal, SID is read channel signal, CLK is clock signal, unit 412-iCMD is alignment data strobing signal); and a read data strobing signal transmission circuit configured to generate a read data strobing signal, based on the alignment data strobing signal (base die 410 generate read data strobing signal RDQS and data signal DQ by the unit 414 / 415 based on data signal “DATA” which is controlled by alignment data strobing signal command iCMD received by decoder unit 431/421 to align with I/O circuitry output) and transmit the read data strobing signal to the base die and wherein the read data strobing signals generated from the core dies forming the same rank among the plurality of core dies are transmitted to the base die through the same through via arrays (see Fig. 1-2, 11-16, 18 and paragraph 0006-0009, 0034-0043, 0054-0056, 0122-0133, 0137-0154, 0158-0175, DATA is output based on iCMD signal and RDQS from controller 100 to core die 420, 430).
Even though Moon et al. teach base die 310, 410, 1110, core die 420, 430 and core data “DATA” but silent exclusively about via arrays. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Moon et al. where core die receive the iCMD signal from base die through vias (TSV-see paragraph 0123) i.e. multiple vias which would be called via arrays in order to improve reliability of read data strobe signal (see paragraph 0199).
Regarding claim 31, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 30 on which this claim depends.
Moon et al. further teach, wherein the read data strobing signal transmission circuit includes: a transmission activation signal generation circuit configured to generate a transmission activation signal activated during a transmission period, based on the alignment data strobing signal; and a read data strobing signal generation circuit configured to generate the read data strobing signal according to the alignment data strobing signal during the transmission period in which the transmission activation signal is activated (see Fig. 1-2, 11-16, 18 and paragraph 0006-0009, 0034-0043, 0054-0056, 0122-0133, 0137-0154, 0158-0175-414 is transmitter).
Regarding claim 32, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 30 on which this claim depends.
Moon et al. further teach, wherein when the alignment data strobing signal includes first to sixth alignment data strobing signals, the transmission activation signal includes first to fourth transmission activation signals, and the read data strobing signal includes first to fourth read data strobing signals, the transmission activation signal generation circuit is configured to: generate the first transmission activation signal activated during a first transmission period in which the first alignment data strobing signal and the third alignment data strobing signal are generated (see Fig. 1-2, 11-16, 18 and paragraph 0006-0009, 0034-0043, 0054-0056, 0122-0133, 0137-0154, 0158-0175, 414 is transmitter), generate the second transmission activation signal activated during a second transmission period in which the second alignment data strobing signal and the fourth alignment data strobing signal are generated, generate the third transmission activation signal activated during a third transmission period in which the third alignment data strobing signal and the fifth alignment data strobing signal are generated, and generate the fourth transmission activation signal activated during a fourth transmission period in which the fourth alignment data strobing signal and the sixth alignment data strobing signal are generated (see Fig. 1-2, 11-16, 18 and paragraph 0006-0009, 0034-0043, 0054-0056, 0122-0133, 0137-0154, 0158-0175, where transmitter 414 generate first, second, third signal).
Regarding claim 33, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 32 on which this claim depends.
Moon et al. further teach, wherein the read data strobing signal generation circuit is configured to: output the first alignment data strobing signal as the first read data strobing signal during the first transmission period, output the second alignment data strobing signal as the second read data strobing signal during the second transmission period, output the third alignment data strobing signal as the third read data strobing signal during the third transmission period, and output the fourth alignment data strobing signal as the fourth read data strobing signal during the fourth transmission period (see Fig. 1-2, 11-16, 18 and paragraph 0006-0009, 0034-0043, 0054-0056, 0122-0133, 0137-0154, 0158-0175, where transmitter 414 generate first, second, third signal).
Allowable Subject Matter
Claims 11-20, 22-29, 34-36 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 11 include allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having:
wherein the alignment data strobing signal generation circuit includes a latch signal generation circuit configured to generate a latch identification signal, an inverted latch identification signal, a latch channel signal, and an inverted latch channel signal, based on the internal clock signal, the read identification signal, and the read channel signal.
Claim 22 include allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having:
generate a latch identification signal and a latch channel signal from the read identification signal and the read channel signal in-phase with the internal clock signal, and generate the alignment data strobing signal, based on the latch identification signal, the latch channel signal, and a core identification signal, and generate an inverted latch identification signal and an inverted latch channel signal from the read identification signal and the read channel signal out-phase with the internal clock signal, and generate the alignment data strobing signal, based on the inverted latch identification signal, the inverted latch channel signal, and the core identification signal.
Claim 34 include allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having:
wherein the plurality of channels form a first rank and a second rank for setting bandwidth, and wherein the memory device is configured to: receive an internal clock signal. read identification signal, and a read channel signal to generate a first alignment data strobing signal from the internal clock signal, based on the read identification signal and the read channel signal, and generate a first read data strobing signal from the first alignment data strobing signal during a first transmission period, based on the first alignment data strobing signal, when a read operation on the first pseudo channel of the first rank is performed, and generate a second alignment data strobing signal from the internal clock signal, based on the read identification signal and the read channel signal, and generate a second read data strobing signal from the second alignment data strobing signal during a second transmission period, based on the second alignment data strobing signal, when a read operation on the first pseudo channel of the second rank is performed.
Claim 35 include allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having:
wherein the plurality of channels form a first rank and a second rank for setting bandwidth, and wherein the memory device is configured to: receive an internal clock signal. read identification signal, and a read channel signal to generate a first alignment data strobing signal from the internal clock signal, based on the read identification signal and the read channel signal, and generate a first read data strobing signal from the first alignment data strobing signal during a first transmission period, based on the first alignment data strobing signal, when a read operation on the first pseudo channel of the first rank is performed, and generate a second alignment data strobing signal from the internal clock signal, based on the read identification signal and the read channel signal, and generate a second read data strobing signal from the second alignment data strobing signal during a second transmission period, based on the second alignment data strobing signal, when a read operation on the second pseudo channel of the second rank is performed.
Claim 36 include allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having:
wherein the plurality of channels form a rank for setting a bandwidth, and wherein the memory device is configured to: receive an internal clock signal, read identification signal, and a read channel signal to generate a first alignment data strobing signal from the internal clock signal, based on the read identification signal and the read channel signal, and generate a first read data strobing signal from the first alignment data strobing signal during a first transmission period, based on the first alignment data strobing signal, when a read operation on the first pseudo channel of the rank is performed, and generate a second alignment data strobing signal from the internal clock signal, based on the read identification signal and the read channel signal, and generate a second read data strobing signal from the second alignment data strobing signal during a second transmission period, based on the second alignment data strobing signal, when a read operation on the second pseudo channel of the rank is performed.
Response to Arguments
Applicant's arguments filed 06/06/2026 have been fully considered but they are not persuasive.
Applicant argues (see page 24 of remarks) that Moon fails to teach or suggest "an alignment data strobing signal generation circuit configured to receive a read identification signal, read channel signal, and internal clock signal and to generate an alignment data strobing signal from the internal clock signal" as set forth in claim 1. Examiner respectfully disagrees with this statement.
First, as per claim 1, the limitation “generate an alignment data strobing signal” clearly indicate just a signal to align with data strobe signal which would be read strobe / write strobe signal. Here, limitation “align” would be interpreted broadly as the claim limitation didn’t specify it.
Second, limitation “internal clock signal” indicate internally generated clock signal which can be from memory controller.
Especially in Fig. 14, paragraph 0147-0154, Moon et al. teach the signal iCMD was generated based on command signal CMD (read / write command), Channel signal SID and clock signal CLK. Based on Fig.1, CLK signal was generated from memory controller 100. So, CLK signal is internal clock signal.
Moon et al. further teach that command decoder 431 receive the iCMD signal and control the I/O circuitry 432 i.e. data I/O circuitry control / align the write strobe data to memory or read strobe data from memory based on iCMD signal which would be called alignment data strobe signal (notice “DATA” signal is bidirectional and “iCMD” signal is unidirectional).
Applicant argues (see page 24 of remarks) that Moon fails to teach or suggest "a core pipe configured to receive the alignment data strobing signal and to output core data output from the specific pseudo channel, based on the alignment data strobing signal" as set forth in claim 1. Examiner respectfully disagrees with this statement.
First, here the limitation “core pipe” is broad and as per claim limitation, it receive alignment data strobing signal and output core data, i.e. any signal line / pipe for the core die receives alignment data strobing signal and output core data would be called core pipe.
Second, limitation “core data” would be interpreted data from core die.
Especially in Fig. 14, paragraph 0147-0154, Moon et al. teach, internal signal iCMD received by the core die 430 / 420 through 402 channel / line / pipe and output core data as “DATA” by the I/O circuitry 432/422. So, signal line 402 would be called core pipe line.
Applicant argues (see page 25 of remarks) that Moon fails to teach or suggest "a read data strobing signal transmission circuit configured to generate a read data strobing signal, based on the alignment data strobing signal" as set forth in claim 30. Examiner respectfully disagrees with this statement.
Especially in Fig. 14, paragraph 0147-0154, Moon et al. teach base die 410 generate read data strobing signal RDQS and data signal DQ by the unit 414 / 415 based on also data signal “DATA” which is controlled by alignment data strobing signal command iCMD received by decoder unit 431/421 to align with I/O circuitry output “DATA”.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277 and fax number is (571)273-2908. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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