DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Foreign priority is not claimed for this application.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: Package 300 mentioned in paragraph 35 in relation to figure 3 is not shown. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-15 of U.S. Patent No. 12,028,022. Although the claims at issue are not identical, they are not patentably distinct from each other because they both refer to the same field of invention: two amplifiers on separate substrates.
As set forth below, the chart identifies which claims from the current application corresponds to conflicting claims found in the cited US Patent.
Current Application
US Patent 12,028,022
21
1
22
2
23
3
24
4
25
5
26
6
27
7
28
8
29
9
30
10
31
11
32
12
33
13
34
14
35
15
36
7
37
9
38
10
39
13
40
14
As disclosed in the chart above, the US patent claims 1-15 substantially recite the same limitations recited in claims 21-40 or the current application as listed above. The only differences are that the current application provides broader claim language. Independent claim 21 recites “an amplifier circuit” and “a second amplifier circuit” which can be mapped to a peaking amplifier and a main amplifier of claim 1 of the patent. Claim 21 also recites the amplifier is formed on a silicon substrate whereas the second amplifier is on a substrate that’s not silicon; the patent recites in claim 1 that the peaking amplifier is formed on a silicon substrate and the main amplifier is formed on a silicon carbide substrate, which is different from silicon and therefore substantially the same as claim 21. The rest of the claims in the current application and patent follow a similar pattern.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 21-22, 27, 29-30, and 36-38 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 20150333706 by Blednov.
Regarding claim 21, Blednov teaches a power amplifier (Figs. 1, 2b) for amplifying an input signal (10) to an output signal (20) comprising:
an amplifier circuit (30, Par. 37), wherein the amplifier circuit is formed in gallium nitride materials on a silicon substrate (Par. 106: the amplifier can be gallium nitride on a silicon substrate); and
a second amplifier circuit (40, Par. 37), wherein the second amplifier circuit is on a substrate that is not silicon (Par. 106: the second amplifier can be on any substrate that’s not silicon).
Regarding claim 22, Blednov teaches the power amplifier according to claim 21, wherein the power amplifier is implemented in a single package (Par. 32).
Regarding claim 27, Blednov teaches the power amplifier according to claim 21, wherein the power amplifier is a Doherty power amplifier (Par. 37).
Regarding claim 29, Blednov teaches a power amplifier (Fig. 1, 2b) for amplifying an input signal (10) to an output signal (20) comprising:
an amplifier circuit (Par. 37), wherein the amplifier circuit is formed in gallium nitride materials on a silicon carbide substrate (Par. 106: the amplifier can be gallium nitride on a silicon carbide substrate); and
a second amplifier circuit (Par. 37), wherein the second amplifier circuit is on a substrate that is not silicon carbide (Par. 106: the second amplifier can be on any substrate that’s not silicon carbide).
Regarding claim 30, Blednov teaches the power amplifier according to claim 29, wherein the power amplifier is implemented in a single package (Par. 32).
Regarding claim 36, Blednov teaches the power amplifier according to claim 29, wherein the power amplifier is a Doherty power amplifier (Par. 37).
Regarding claim 37, Blednov teaches a Doherty power amplifier (Par. 37; Fig. 1, 2b) comprising:
a peaking amplifier circuit (30, 50; Par. 37), wherein the peaking amplifier circuit is formed in gallium nitride materials on a first substrate of a first material composition (Par. 106: the peaking amplifier can be gallium nitride on first substrate of a first material composition); and
a main amplifier circuit (40; Par. 37), wherein the main amplifier circuit is formed in gallium nitride materials on a second substrate of a second material composition different than the first substrate (Par. 106: the main amplifier can be formed on gallium nitride materials on a second substrate that’s different than a first).
Regarding claim 38, Blednov teaches the power amplifier according to claim 37, wherein the power amplifier is implemented in a single package (Par. 32).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 23-24, 28, 31-32, and 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20150333706 by Blednov.
Regarding claim 23, Blednov teaches the power amplifier according to claim 22, and while Blednov does not mention a DFN package, different types of packaging, such as dual flat no-lead packaging, are well known in the art and can be implemented in amplifier circuits, as shown in par. 15 of US 20220130768 by Wei et al.
Regarding claim 24, Blednov teaches the power amplifier according to claim 22, and while Blednov does not mention a QFN package, different types of packaging, such as quad flat no-lead packaging, are well known in the art and can be implemented in amplifier circuits, as shown in par. 15 of US 20220130768 by Wei et al.
Regarding claim 28, Blednov teaches the power amplifier claim according to claim 21, but is silent on the power amplifier being disposed on a printed circuit board (PCB) and a pre-driver amplifier circuit that’s positioned on the PCB and has an output coupled to an input of the power amplifier, the output feeding the amplifier circuit and the second amplifier circuit.
However, these are simply design choices as shown in fig. 2 and par. 31 of US 20130082711 by Albrecht, and a person of ordinary skill in the art could choose to have the power amplifier and pre-driver amplifier circuit on the PCB as it’s common practice and helps with time and manufacturing costs.
Regarding claim 31, Blednov teaches the power amplifier according to claim 30, and while Blednov does not mention a DFN package, different types of packaging, such as dual flat no-lead packaging, are well known in the art and can be implemented in amplifier circuits, as shown in par. 15 of US 20220130768 by Wei et al.
Regarding claim 32, Blednov teaches the power amplifier according to claim 30, and while Blednov does not mention a QFN package, different types of packaging, such as quad flat no-lead packaging, are well known in the art and can be implemented in amplifier circuits, as shown in par. 15 of US 20220130768 by Wei et al.
Regarding claim 35, Blednov teaches the power amplifier claim according to claim 29, but is silent on the power amplifier being disposed on a printed circuit board (PCB) and a pre-driver amplifier circuit that’s positioned on the PCB and has an output coupled to an input of the power amplifier, the output feeding the amplifier circuit and the second amplifier circuit.
However, these are simply design choices as shown in fig. 2 and par. 31 of US 20130082711 by Albrecht, and a person of ordinary skill in the art could choose to have the power amplifier and pre-driver amplifier circuit on the PCB as it’s common practice and helps with time and manufacturing costs.
Claim(s) 25-26, 33-34, and 39-40 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20150333706 by Blednov in further view of US 20160218693 by Lyalin.
Regarding claim 25, Blednov teaches the power amplifier according to claim 22, but fails to teach wherein the single package further comprises a pre-driver amplifier circuit that feeds the amplifier circuit and the second amplifier circuit.
However, Lyalin teaches a Doherty amplifier system on a packaging substrate that’s configured to receive a plurality of components (Par. 11) wherein the single package further comprises a pre-driver amplifier circuit (Fig. 17 #802) that feeds the amplifier circuit (#814) and the second amplifier circuit (#834).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the pre-driver of Lyalin with the power amplifier of Blednov in order to have an amplification circuit that can partially amplify an RF signal before feeding the partially amplified signal to a first and second amplifier (Par. 60) in order to have more gain.
Regarding claim 26, the combination of Blednov and Lyalin teaches the power amplifier according to claim 25, but fails to teach wherein the pre-driver amplifier circuit is formed in gallium nitride materials on a silicon substrate, the pre-driver amplifier circuit being formed on a separate die relative to the amplifier circuit.
However, US 20210194434 by Ladhani et al. teaches an amplifier circuit with a driver stage before the final stage that comprise gallium nitride on a silicon substrate, with the driver stage transistor on a separate die relative to the final stage transistor (Par. 59). This is simply design engineering that can help with optimal circuit performance.
Regarding claim 33, Blednov teaches the power amplifier according to claim 30, but fails to teach wherein the single package further comprises a pre-driver amplifier circuit that feeds the amplifier circuit and the second amplifier circuit.
However, Lyalin teaches a Doherty amplifier system on a packaging substrate that’s configured to receive a plurality of components (Par. 11) wherein the single package further comprises a pre-driver amplifier circuit (Fig. 17 #802) that feeds the amplifier circuit (#814) and the second amplifier circuit (#834).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the pre-driver of Lyalin with the power amplifier of Blednov in order to have an amplification circuit that can partially amplify an RF signal before feeding the partially amplified signal to a first and second amplifier (Par. 60) in order to have more gain.
Regarding claim 34, the combination of Blednov and Lyalin teaches the power amplifier according to claim 33, but fails to teach wherein the pre-driver amplifier circuit is formed in gallium nitride materials on a silicon substrate, the pre-driver amplifier circuit being formed on a separate die relative to the amplifier circuit.
However, US 20210194434 by Ladhani et al. teaches an amplifier circuit with a driver stage before the final stage that comprise gallium nitride on a silicon substrate, with the driver stage transistor on a separate die relative to the final stage transistor (Par. 59). This is simply design engineering that can help with optimal circuit performance.
Regarding claim 39, Blednov teaches the power amplifier according to claim 38, but fails to teach wherein the single package further comprises a pre-driver amplifier circuit that feeds the amplifier circuit and the second amplifier circuit.
However, Lyalin teaches a Doherty amplifier system on a packaging substrate that’s configured to receive a plurality of components (Par. 11) wherein the single package further comprises a pre-driver amplifier circuit (Fig. 17 #802) that feeds the amplifier circuit (#814) and the second amplifier circuit (#834).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the pre-driver of Lyalin with the power amplifier of Blednov in order to have an amplification circuit that can partially amplify an RF signal before feeding the partially amplified signal to a first and second amplifier (Par. 60) in order to have more gain.
Regarding claim 34, the combination of Blednov and Lyalin teaches the power amplifier according to claim 33, but fails to teach wherein the pre-driver amplifier circuit is formed in gallium nitride materials on a silicon substrate, the pre-driver amplifier circuit being formed on a separate die relative to the amplifier circuit.
However, US 20210194434 by Ladhani et al. teaches an amplifier circuit with a driver stage before the final stage that comprise gallium nitride on a silicon substrate, with the driver stage transistor on a separate die relative to the final stage transistor (Par. 59). This is simply design engineering that can help with optimal circuit performance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAREH SHAMIRYAN whose telephone number is (703)756-4616. The examiner can normally be reached M-F: 7:00AM-4:00PM PT.
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/NAREH SHAMIRYAN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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