DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-20 in the reply filed on 01/20/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the second semiconductor chip” in line 4. There is insufficient antecedent basis for said limitation in the claim. Correction is required.
Claims 2-12 are rejected for being dependent on claim 1.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,610,828 (Park et al). Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding claim 1, Park teaches in claims 1 a semiconductor package comprising:
a package substrate;
a semiconductor chip arranged on an upper surface of the package substrate; and
a molding member configured to surround the second semiconductor chip,
wherein the molding member includes a protruding sidewall including an upper end that extends horizontally outward and is vertically offset below an upper surface of the molding member by a first distance, a lower end that extends horizontally outward and is vertically offset above a lower surface of the molding member by a second distance, and an outer side surface vertically extending between the upper end and the lower end.
Claims 2-12 are rejected for being dependent on claim 1.
Regarding claim 13, Park teaches a semiconductor package comprising: a package substrate; an interposer disposed on an upper surface of the package substrate; a first semiconductor chip and at least one second semiconductor chip disposed on an upper surface of the interposer; and a molding member around side surfaces of the first semiconductor chip and the at least one second semiconductor chip, wherein the molding member includes a protruding sidewall including an upper end that extends horizontally outward and is vertically offset below an upper surface of the molding member by a first distance, a lower end that extends horizontally outward and is vertically offset above a lower surface of the molding member by a second distance, and an outer side surface vertically extending between the upper end and the lower end.
Claims 14-20 are rejected for being dependent on claim 13.
Allowable Subject Matter
Claims 1-20 are allowable pending resolution of the doubling-patenting issues and 112 rejection.
The following is an examiner’s statement of reasons for allowance:
With respect to claims 1, the prior art of record fails to teach or suggest in combination of other claim features, a semiconductor package, comprising: a molding member configured to surround the second semiconductor chip, wherein the molding member includes a protruding sidewall including an upper end that extends horizontally outward and is vertically offset below an upper surface of the molding member by a first distance, a lower end that extends horizontally outward and is vertically offset above a lower surface of the molding member by a second distance, and an outer side surface vertically extending between the upper end and the lower end.
Claims 2-12 are allowable as being directly or indirectly dependent of the allowed independent base claim 1.
With respect to claims 13, the prior art of record fails to teach or suggest in combination of other claim features, a semiconductor package, comprising: a molding member around side surfaces of the first semiconductor chip and the at least one second semiconductor chip, wherein the molding member includes a protruding sidewall including an upper end that extends horizontally outward and is vertically offset below an upper surface of the molding member by a first distance, a lower end that extends horizontally outward and is vertically offset above a lower surface of the molding member by a second distance, and an outer side surface vertically extending between the upper end and the lower end.
Claims 14-20 are allowable as being directly or indirectly dependent of the allowed independent base claim 13.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TIMOR KARIMY/Primary Examiner, Art Unit 2818
Prosecution Insights