Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
Applicant' s amendment dated 04/21/2026 in which claims 1, 10 and 19 were amended has been entered of record. Currently, claims 1-20 are pending in light of the amendment.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Aritome (Patent Application Publication 2013/0010547).
Claim 1. A method of operating a memory device, comprising: applying a first read voltage to a first word line WLn corresponding to target memory cells (Vpgm Aritome Fig 4, WLn Fig 3) during a first period (Vpgm is applied during the period of 1-25 supplied pulses); applying a first pass voltage to a second word line WLn-1 corresponding to memory cells adjacent to the target memory cells (Vpass1 Fig 4, WLn-1 Fig 3) during the first period (Vpass1 is applied during the period of 1-25 supplied pulses); and applying a second pass voltage to a third word line WLn+1 corresponding to memory cells adjacent to the target memory cells (Vpass2 Fig 4, WLn-1, Fig 3) during the first period (Vpass2 is applied during the period of 1-25 supplied pulses), wherein the second pass voltage is higher than the first pass voltage (Vpass2 is higher than Vpass1 Fig 4).
Claim 2. The method of claim 1, wherein in a forward programming scheme or a reverse programming scheme, the second word line WLn-1 (WLn-1 Fig 3), the first word line WLn (WLn Fig 3), and the third word line WLn+1 (WLn+1 Fig 3) are applied with program voltages in sequence (application of voltages taught in Aritome Fig 4).
Claim 3. The method of claim 2, wherein in the forward programming scheme, the second word line WLn-1 (WLn-1 Fig 3) is closer to a source select gate of a memory string of the memory device than the third word line WLn+1 (seen closer to SSL than WLn+1, Fig 3).
Claim 4. The method of claim 2, wherein in the reverse programming scheme, the third word line WLn+1 (WLn+1 Fig 3) is closer to a source select gate of a memory string of the memory device than the second word line WLn-1 (seen closer to DSL than WLn-1, Fig 3).
Claim 5. The method of claim 1, wherein the second pass voltage is between 7V and 9V (Fig 2 teaches Vpass2 between 7V and 9V).
Claim 6. The method of claim 1, wherein the first pass voltage is between 6V and 8V (Fig 5 teaches Vpass1 between 6V and 8V).
Claim 7. The method of claim 1, further comprising: applying a third pass voltage to a fourth word line WLn-2 (WLn-2 Fig 3 Vpass3 Fig 5); and applying a fourth pass voltage to a fifth word line WLn+2 (WLn+2 Fig 3 Vpass4 Fig 6), wherein the third pass voltage is equal to or lower than the first pass voltage (Vpass3 is equal or lower than Vpass1 as seen in Fig 6).
Claim 8. The method of claim 7, wherein the fourth pass voltage is lower than the second pass voltage (Vpass4 is lower than Vpass2 as seen in Fig 6).
Claim 9. The method of claim 7, wherein the fourth pass voltage is higher than the first pass voltage (Choosing Vpass11 as the first pass voltage, Vpass4 is higher than Vpass11 as seen in Fig 6).
Claim 10. A memory device, comprising: a memory cell array comprising memory cells; and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to (functional language): apply a first read voltage to a first word line WLn corresponding to target memory cells (Vpgm Aritome Fig 4, WLn Fig 3) during a first period (Vpgm is applied during the period of 1-25 supplied pulses); apply a first pass voltage (Vpass1) to a second word line WLn-1 corresponding to memory cells adjacent to the target memory cells (WLn-1, Aritome Fig 3) during the first period (Vpass1 is applied during the period of 1-25 supplied pulses); and apply a second pass voltage to a third word line WLn+1 corresponding to memory cells adjacent to the target memory cells (Vpass2 Fig 4, WLn-1, Fig 3) during the first period (Vpass2 is applied during the period of 1-25 supplied pulses), wherein the second pass voltage is higher than the first pass voltage (Vpass2 is higher than Vpass1 Fig 4).
Claim 11. The memory device of claim 10, wherein in a forward programming scheme or a reverse programming scheme, the second word line WLn-1 (WLn-1 Fig 3), the first word line WLn (WLn Fig 3), and the third word line WLn+1 (WLn+1 Fig 3) are applied with program voltages in sequence (application of voltages taught in Aritome Fig 4).
Claim 12. The memory device of claim 11, wherein in the forward programming scheme, the second word line WLn-1 (WLn-1 Fig 3) is closer to a source select gate of a memory string of the memory device than the third word line WLn+1 (seen closer to SSL than WLn+1, Fig 3).
Claim 13. The memory device of claim 11, wherein in the reverse programming scheme, the third word line WLn+1 is closer to a source select gate of a memory string of the memory device than the second word line WLn-1.
Claim 14. The memory device of claim 10, wherein the second pass voltage is between 7V and 9V (Fig 2 teaches Vpass2 between 7V and 9V).
Claim 15. The memory device of claim 10, wherein the first pass voltage is between 6V and 8V (Fig 5 teaches Vpass1 between 6V and 8V).
Claim 16. The memory device of claim 10, wherein the peripheral circuit is configured to (functional language): apply a third pass voltage to a fourth word line WLn-2 (WLn-2 Fig 3 Vpass3 Fig 5); and apply a fourth pass voltage to a fifth word line WLn+2 (WLn+2 Fig 3 Vpass4 Fig 6), wherein the third pass voltage is equal to or lower than the first pass voltage (Vpass3 is equal or lower than Vpass1 as seen in Fig 6).
Claim 17. The memory device of claim 16, wherein the fourth pass voltage is lower than the second pass voltage (Vpass4 is lower than Vpass2 as seen in Fig 6).
Claim 18. The memory device of claim 16, wherein the fourth pass voltage is higher than the first pass voltage (Choosing Vpass11 as the first pass voltage, Vpass4 is higher than Vpass11 as seen in Fig 6).
Claim 19. A memory system, comprising: a memory device (comprising 110 Aritome Fig 3); and a memory controller coupled to the memory device (120 Fig 3), wherein the memory device comprises: a memory cell array comprising memory cells (array in 110 Aritome Fig 3); and a peripheral circuit coupled to the memory cell array (as seen in Fig 3), wherein the peripheral circuit is configured to (functional language): apply a first read voltage to a first word line WLn corresponding to target memory cells (Vpgm Aritome Fig 4, WLn Fig 3) during a first period (Vpgm is applied during the period of 1-25 supplied pulses); apply a first pass voltage to a second word line WLn-1 corresponding to memory cells adjacent to the target memory cells (Vpass1 Fig 4, WLn-1 Fig 3) during the first period (Vpass1 is applied during the period of 1-25 supplied pulses); and apply a second pass voltage to a third word line WLn+1 corresponding to memory cells adjacent to the target memory cells (Vpass2 Fig 4, WLn-1, Fig 3) during the first period (Vpass2 is applied during the period of 1-25 supplied pulses), wherein the second pass voltage is higher than the first pass voltage (Vpass2 is higher than Vpass1 Fig 4).
Claim 20. The memory system of claim 19, wherein the peripheral circuit is configured to (functional language): apply a third pass voltage to a fourth word line WLn-2 (WLn-2 Fig 3 Vpass3 Fig 5); and apply a fourth pass voltage to a fifth word line WLn+2 (WLn+2 Fig 3 Vpass4 Fig 6), wherein the third pass voltage is equal to or lower than the first pass voltage (Vpass3 is equal or lower than Vpass1 as seen in Fig 6).
Response to Arguments
Applicant's arguments with respect to claims 1, 10 and 19 have been considered but are moot in view of the new ground(s) of rejection.
Newly amended claims 1, 10 and 19 with respect to a time period are addressed in the 102 above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Lappas whose telephone number is (571) 270-1272. The examiner can normally be reached on M-F 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON LAPPAS/Primary Examiner, Art Unit 2827
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