DETAILED ACTION
Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li, U.S. Pub No. 20220319422.
Regarding claim 1, Li discloses a display panel (Li discloses a display substrate and display device including array of pixels), comprising (See Figs. 3B-7B, [0212]-[0216]):
a substrate plate 101,
light-emitting elements 10 (Fig. 3B) and pixel driving circuits (driving transistor, capacitors), wherein the pixel driving circuits are electrically connected to the light-emitting elements (Fig. 3B: pixel circuit and light-emitting element connected by: driving circuit 112/driving transistor N2 electrically connected t light-emitting element 120 [0086]),
first power signal lines (power lines 280a and 280b; [0213]-[0214]) electrically connected to the pixel driving circuits (280a is electrically connected through connection electrode 318 of driving transistor N2; used to transmit the first power voltage VDD, Fig. 7A), and
second power signal lines (power lines 270a and 270b, [0013], transmit second power voltage VSS, Fig. 7A), wherein the second power signal lines and the first power signal lines are located in a first conductor layer (the second conductive layer 302 includes power lines 270a, 270b, 280a, 280b; Fig. 3B) and have substantially same line shapes (Fig. 7A: 270a/270b and 280a/280b are substantially elongated rectangular lines extending along D1, and symmetrical pattern in conductive layer 302, [0212]-[0214]).
Regarding claim 2, Li discloses wherein the second power signal lines at least include common power signal lines, and the common power signal lines are electrically connected to the light-emitting elements (power lines 270a/270b transmitting second power voltage VSS [0213]-[0214], first common voltage Vcom1 is supplied to second electrode 122 of light-emitting element 120, [0086]).
Regarding claim 6, Li discloses wherein:
at least three pixel driving circuits form a pixel driving circuit group (plurality of subpixels/pixel rows, Fig. 3B, 7A),
different pixel driving circuits in one same pixel driving circuit group are electrically connected to the light emitting elements of different colors respectively,
the first conductor layer also includes first reference power signal lines ([0030]-[0031], first power lines and second power lines are in the same second conductive layer),
the first reference power signal lines (first power lines) are electrically connected to the pixel driving circuits [0030],
the first reference power signal lines, the second power lines and first power signal lines all extend along a first direction (first power lines and second power lines extend along first direction D1 [0030]-[0031], [0213]),
along a second direction, one first reference power signal line is provided at an interval of every N2 pixel driving circuit groups, wherein N2 is an integer larger than or equal to 0 (repeating arrangement, [0030]-[0034]), and the second direction intersects the first direction (D1 and D2 Fig. 7A show them perpendicular).
Regarding claim 7, Li discloses wherein the second power signal lines 280/VDD further include first reference power signal lines , and the first reference power signal lines are electrically connected to the pixel driving circuits ([0030]-[0034]: first, second, third, fourth, fifth and sixth power lines, and the first power line can be reference power signal line).
Regarding claim 8, Li discloses further including an active layer wherein the active layer includes second reference power signal lines, and the second reference power signal lines are electrically connected to the first reference power signal lines ([0213], 270a is connected with power line 260 in first conductive layer 301, and 270a is in second conductive layer 302 and carries VSS).
Regarding claim 15, Li discloses a display panel (Li discloses a display substrate and display device including array of pixels), comprising (See Figs. 3B-7B, [0212]-[0216]):
a substrate plate 101,
light-emitting elements 10 (Fig. 3B) and pixel driving circuits (driving transistor, capacitors), wherein the pixel driving circuits are electrically connected to the light-emitting elements (Fig. 3B: pixel circuit and light-emitting element connected by: driving circuit 112/driving transistor N2 electrically connected t light-emitting element 120 [0086]),
first power signal lines (power lines 280a and 280b; [0213]-[0214]) electrically connected to the pixel driving circuits (280a is electrically connected through connection electrode 318 of driving transistor N2; used to transmit the first power voltage VDD, Fig. 7A), and
second power signal lines (power lines 270a and 270b, [0013], transmit second power voltage VSS, Fig. 7A), wherein the second power signal lines and the first power signal lines are located in a first conductor layer (the second conductive layer 302 includes power lines 270a, 270b, 280a, 280b; Fig. 3B) and have substantially same line shapes (Fig. 7A: 270a/270b and 280a/280b are substantially elongated rectangular lines extending along D1, and symmetrical pattern in conductive layer 302, [0212]-[0214]).
Regarding claim 16, Li discloses wherein the second power signal lines at least include common power signal lines, and the common power signal lines are electrically connected to the light-emitting elements (power lines 270a/270b transmitting second power voltage VSS [0213]-[0214], first common voltage Vcom1 is supplied to second electrode 122 of light-emitting element 120, [0086]).
Regarding claim 19, Li discloses wherein:
at least three pixel driving circuits form a pixel driving circuit group (plurality of subpixels/pixel rows, Fig. 3B, 7A),
different pixel driving circuits in one same pixel driving circuit group are electrically connected to the light emitting elements of different colors respectively,
the first conductor layer also includes first reference power signal lines ([0030]-[0031], first power lines and second power lines are in the same second conductive layer),
the first reference power signal lines (first power lines) are electrically connected to the pixel driving circuits [0030],
the first reference power signal lines, the second power lines and first power signal lines all extend along a first direction (first power lines and second power lines extend along first direction D1 [0030]-[0031], [0213]),
along a second direction, one first reference power signal line is provided at an interval of every N2 pixel driving circuit groups, wherein N2 is an integer larger than or equal to 0 (repeating arrangement, [0030]-[0034]), and the second direction intersects the first direction (D1 and D2 Fig. 7A show them perpendicular).
Regarding claim 20, Li discloses wherein the second power signal lines 270/VDD further include second reference power signal lines , and the second reference power signal lines are electrically connected to the pixel driving circuits ([0030]-[0034]: first, second, third, fourth, fifth and sixth power lines, and the first power line can be reference power signal line).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Li, U.S. Pub No. 20220319422
Regarding claim 13, Li fails to disclose a density of the second power signal lines in the central display area is smaller than or equal to a density of the second power signal lines in the edge displayer area, and/or, a line width of the second power signal lines in the central display area is smaller than or equal to a line width of the second power signal lines in the edge display area. However, the selection of such parameters such as energy, concentration, temperature, time, molar fraction, depth, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc., or in conbination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art ... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Allowable Subject Matter
Claims 3-5, 9-12 are objected.
Claims 3-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitations according to claim 1-2, among other limitations cited in claim 3, and along a direction perpendicular to a plane where the substrate plate is located, different pixel driving circuits in one same pixel driving circuit group overlap with different power signal lines respectively, and among at least three power signal lines corresponding to one same pixel driving circuit group, at least one power signal line is set as the first power signal lines and at least one other power signal line is set as the common power signal line.
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitations according to claim 1-2, among other limitations cited in claim 5, along a second direction, each pixel driving circuit group is provided with one common power signal line or one common power signal line is provided at an interval of every N1 pixel circuit groups, wherein N1 is an integer larger than 0 and the second direction intersects the first direction.
Claims 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitations according to claim 9-10, among other limitations cited in claim 7, and along a direction perpendicular to a plane where the substrate plate is located, different pixel driving circuits in one same pixel driving circuit group overlap with different power signal lines respectively, and among at least three power signal lines corresponding to one same pixel driving circuit group, at least one power signal line is set as the first power signal lines and at least one other power signal line is set as the common power signal line.
Claims 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitations according to claim 1-2, among other limitations cited in claim 3, and along a direction perpendicular to a plane where the substrate plate is located, different pixel driving circuits in one same pixel driving circuit group overlap with different power signal lines respectively, and among at least three power signal lines corresponding to one same pixel driving circuit group, at least one power signal line is set as the first power signal lines and at least one other power signal line is set as the common power signal line.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAO P LE whose telephone number is (571)272-1785. The examiner can normally be reached on Monday-Friday 9AM-6PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/THAO P LE/Primary Examiner, Art Unit 2818
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