DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
2. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Memory Devices, Systems, and Operation Methods Managing Multiple Pages of Data”
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 1-16 and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, in line 3, recites the limitation, “word lines each coupled to corresponding memory cell in each memory string,” which is indefinite. Examiner believes the limitation should recite either “word lines, each coupled to corresponding memory [[cell]] cells in each memory string,” or “word lines, each coupled to a corresponding memory cell in each memory string.” For the purpose of this action, the limitation, “word lines each coupled to corresponding memory cell in each memory string,” shall be interpreted as, “word lines, each coupled to a corresponding memory cell in each memory string.” Claims 2-16 depend on claim 1.
Claim 2 recites the limitation "the p pages" in line 9. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, the limitation, "the p pages," shall be interpreted as "the at least p pages,” which finds antecedent basis in claim 1, line 8. Claims 6-8 and 12 depend on claim 2.
Claim 3 recites the limitation "the p pages" in line 4. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, the limitation, "the p pages," shall be interpreted as "the at least p pages,” which finds antecedent basis in claim 1, line 8. Claims 9 and 13 depend on claim 2.
Claim 8 recites the limitation, “wherein one memory cell coupled to the second word line stores N-bit data after programming is completed,” which is indefinite.
This limitation finds antecedent basis in ¶[0011] and ¶[0096]. Firstly, however, it is not clear if “one memory cell” in the disclosure is intended to mean “only one memory cell” or “at least one memory cell.” Secondly, if N-bit data is stored to “one memory cell,” it is unclear how many bits are stored to each of the remaining cells coupled to the second word line. Thirdly, it is unclear why there is a correlation between the number of pages (here, N) being programmed and the number of bits per cell (“N-bit data”).
Claim 9 recites the limitation, “wherein one memory cell coupled to the second word line stores p-bit data after programming is completed,” which is indefinite.
This limitation finds antecedent basis in ¶[0012] and ¶[0099-0100]. Firstly, however, it is not clear if “one memory cell” in the disclosure is intended to mean “only one memory cell” or “at least one memory cell.” Secondly, if p-bit data is stored to “one memory cell,” it is unclear how many bits are stored to each of the remaining cells coupled to the second word line. Thirdly, it is unclear why there is a correlation between the number of pages (here, p) being programmed and the number of bits per cell (“p-bit data”).
Claim 10 recites the limitation, “wherein one memory cell coupled to the first word line stores N-bit data after programming is completed,” which is indefinite.
This limitation finds antecedent basis in ¶[0013] and ¶[0104-0105]. Firstly, however, it is not clear if “one memory cell” in the disclosure is intended to mean “only one memory cell” or “at least one memory cell.” Secondly, if N-bit data is stored to “one memory cell,” it is unclear how many bits are stored to the remaining cells coupled to the first word line. Thirdly, it is unclear why there is a correlation between the number of pages (here, N) being programmed and the number of bits per cell (“N-bit data”).
Claim 11 recites the limitation, “wherein one memory cell coupled to the first word line stores m-bit data after programming is completed,” which is indefinite.
This limitation finds antecedent basis in ¶[0014] and ¶[0107-0109]. Firstly, however, it is not clear if “one memory cell” in the disclosure is intended to mean “only one memory cell” or “at least one memory cell.” Secondly, if m-bit data is stored to “one memory cell,” it is unclear how many bits are stored to the remaining cells coupled to the first word line. Thirdly, it is unclear why there is a correlation between the number of pages (here, m) being programmed and the number of bits per cell (“m-bit data”).
Claim 16 recites the limitation "the p pages" in line 6. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, the limitation, "the p pages," shall be interpreted as "the at least p pages,” which finds antecedent basis in claim 1, line 8.
Claim 18, in line 8-9, recites the limitation, “the memory device comprises a block comprising memory strings, wherein each memory string comprises memory cells,” which is indefinite. Examiner believes “memory strings” in the line 8 are the same memory strings as in lines 4 and 6 of claim 18. For the purpose of this action, the limitation, “the memory device comprises a block comprising memory strings, wherein each memory string comprises memory cells” in line 8 shall be interpreted as, “the memory device comprises a block comprising the memory strings, wherein each of the memory strings comprises memory cells.” Claims 19-20 depend on claim 18.
Claim 19 recites the limitation "the p pages" in line 9. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, the limitation, "the p pages," shall be interpreted as "the at least p pages,” which finds antecedent basis in claim 18, line 5.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1 and 16-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim, et al (US 20240194275 A1), hereinafter Kim.
Regarding independent claim 1, Kim teaches a memory device (FIG. 1, 100), comprising:
a block (FIG. 1, BLK1..BLKz) comprising memory strings (FIG. 2, ST1) each comprising memory cells (FIG. 2, MC1..MCn+1);
word lines (FIG. 2, WL1..WLn+1) each coupled to corresponding memory cell in each memory string (FIG. 2 shows WLs coupled to MCs in ST1); and
a peripheral circuit (FIG. 1, 120; ¶[0023]) coupled to the word lines (FIG. 1, RL; ¶[0022] teaches “The row line RL may include…a word line…”) and configured to:
receive a first set of write data comprising N pages of data (FIG. 7, S810, data for Jth and (J+1)th pages are received; N=3);
execute a first program operation to write m pages of data comprised in the first set of write data to memory cells of the memory strings coupled to a first word line (FIG. 7, S831; (J+1)th page programmed, e.g., to WL2 as shown in the “location” column of FIG. 6, “start stage” row; ¶[0068]; m=1); and
execute a second program operation to write at least p pages of data comprised in the first set of write data to memory cells of the memory strings coupled to a second word line (FIG. 7, S851; Jth page programmed, e.g., to WL1 as shown in the “location” column of FIG. 6, “start stage” row; ¶[0068]; p=2), wherein a sum of m and p equals N (m=1, p=2, N=3).
Regarding claim 16, Kim teaches the limitations of claim 1.
Kim further teaches the peripheral circuit is further configured to:
execute a read operation in response to a read command (¶[0115] teaches “When a read command for reading any one page data is received, the control logic 130 may control the peripheral circuit 120 to read page data of a corresponding page, based on the map information”), so as to obtain first read data from the memory cells of the memory strings coupled to the first word line, and to obtain second read data from the memory cells of the memory strings coupled to the second word line (reads of word lines may be done in any order – see, e.g., ¶[0023], [0116]); and
the first read data comprises the m pages of data comprised in the first set of write data ((J+1)th page programmed, e.g., to WL2 as shown in the “location” column of FIG. 6, “start stage” row; m=1); and the second read data comprises the p pages of data comprised in the first set of write data (Jth page programmed, e.g., to WL1 as shown in the “location” column of FIG. 6, “start stage” row; p=2).
Regarding independent claim 17, Kim teaches a memory system (FIG. 1), comprising:
a memory controller (FIG. 1, 200) configured to send a first set of write data comprising N pages of data (¶[0030] teaches data are received from controller 200; FIG. 7, S810, data for Jth and (J+1)th pages are received; N=3); and
a memory device (FIG. 1, 100) coupled to the memory controller and comprising:
a block (FIG. 1, BLK1..BLKz) comprising memory strings (FIG. 2, ST1), wherein each memory string comprises memory cells (FIG. 2, MC1..MCn+1);
word lines (FIG. 2, WL1..WLn+1), wherein each word line is coupled to a corresponding memory cell in each memory string (FIG. 2 shows WLs coupled to MCs in ST1); and
a peripheral circuit (FIG. 1, 120; ¶[0023]) coupled to the word lines (FIG. 1, RL; ¶[0022] teaches “The row line RL may include…a word line…”) and configured to:
receive the first set of write data comprising the N pages of data (FIG. 7, S810, data for Jth and (J+1)th pages are received; N=3);
execute a first program operation to write m pages of data comprised in the first set of write data to memory cells of the memory strings coupled to a first word line (FIG. 7, S831; (J+1)th page programmed, e.g., to WL2 as shown in the “location” column of FIG. 6, “start stage” row; ¶[0068]; m=1); and
execute a second program operation to write at least p pages of data comprised in the first set of write data to memory cells of the memory strings coupled to a second word line (FIG. 7, S851; Jth page programmed, e.g., to WL1 as shown in the “location” column of FIG. 6, “start stage” row; ¶[0068]; p=2), wherein a sum of m and p equals N (m=1, p=2, N=3).
Regarding independent claim 18, Kim teaches a method of operating a memory device (FIG. 7), comprising:
receiving a first set of write data comprising N pages of data (FIG. 7, S810, data for Jth and (J+1)th pages are received; N=3);
executing a first program operation to write m pages of data comprised in the first set of write data to memory cells of memory strings coupled to a first word line (FIG. 7, S831; (J+1)th page programmed, e.g., to WL2 as shown in the “location” column of FIG. 6, “start stage” row; ¶[0068]; m=1); and
executing a second program operation to write at least p pages of data comprised in the first set of write data to memory cells of the memory strings coupled to a second word line, wherein a sum of m and p equals N (FIG. 7, S851; Jth page programmed, e.g., to WL1 as shown in the “location” column of FIG. 6, “start stage” row; ¶[0068]; p=2), wherein a sum of m and p equals N (m=1, p=2, N=3),
wherein the memory device comprises a block (FIG. 1, BLK1..BLKz) comprising memory strings (FIG. 2, ST1), wherein each memory string comprises memory cells (FIG. 2, MC1..MCn+1); and
word lines (FIG. 2, WL1..WLn+1), wherein each word line is coupled to a corresponding memory cell in each memory string (FIG. 2 shows WLs coupled to MCs in ST1).
Allowable Subject Matter
7. Claims 2-15 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
8. The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 2, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein the first word line is adjacent to the second word line, and the second word line is not the first one among word lines to be programed in the block; and the peripheral circuit is further configured to:
execute the second program operation to write the m pages of data comprised in the second set of write data and the p pages of data comprised in the first set of write data to the memory cells of the memory strings coupled to the second word line. Claims 6-8 and 12 depend on claim 2.
Regarding claim 3, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein the first word line is adjacent to the second word line, and the second word line is the first one among word lines to be programed in the block; and the peripheral circuit is further configured to:
execute the second program operation to only write the p pages of data comprised in the first set of write data to the memory cells of the memory strings coupled to the second word line. Claims 9 and 13 depend on claim 3.
Regarding claim 4, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein the first word line is adjacent to the second word line, and the first word line is not the last one among word lines to be programed in the block; and the peripheral circuit is further configured to:
execute a third program operation to write p pages of data comprised in the third set of write data and the m pages of data comprised in the first set of write data to the memory cells of the memory strings coupled to the first word line. Claims 10 and 14 depend on claim 4.
Regarding claim 5, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein the first word line is adjacent to the second word line, and the first word line is the last one among word lines to be programed in the block; and the peripheral circuit is further configured to:
only write the m pages of data comprised in the first set of write data to the memory cells of the memory strings coupled to the first word line. Claims 11 and 15 depend on claim 5.
Regarding claim 19, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of executing the second program operation to write the m pages of data comprised in the second set of write data and the p pages of data comprised in the first set of write data to the memory cells of the memory strings coupled to the second word line.
Regarding claim 20, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of executing the second program operation, to only write the p pages of data comprised in the first set of write data to the memory cells of the memory strings coupled to the second word line.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
Prosecution Insights