Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. The office acknowledges the receipt of the following and placed of record in the file: Amendment dated 3/9/2026.
2. Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Mar et al. (“Mar”), U.S. Patent Publication No. 2002/0087906 and Basile et al. (“Basile”), U.S. Patent Application Publication No. 2016/0048184.
Regarding Claims 1, 8 and 15, Mar teaches an electronic component comprising: a first set of one or more processors [Fig-3(CPUs 330)];
a first power-on control circuitry (control logic 320) to modulate a time (introduce “programmed delay”) to power on the first set of one or more processors responsive to an input (power_good signal) indicating the electronic component to power-up [Para: 0022(“a programmed delay that waits a set time period after the power_good signal has been transmitted to each VRM” so that the “delay VRM permits the VRM to bring its voltage output lines up to appropriate voltage levels and to power-on the processor” in “power_on sequence” as describe in 0026];
a connection to obtain power from a power supply (power supply 305) to power the first set of one or more processors and the first power-on control circuitry (see connection between 305 and control logic 320 - CPU0), wherein the power supply is shared by one or more other electronic components having one or more second sets of one or more processors and the power-on control circuitry [Fig-3(see connection between power supply 305 and logic 320 – CPU 1 or other CPUs)].
Mar does not disclose expressly a second power-on control circuitry associated with the second one or more processors and wherein the first power-on control circuitry modulates the timing of when the first set of one or more processors powers on to differentiate from a timing of when at least some of the one or more second sets of one or more processors power on as controlled by the second power-on control circuitry.
In the same field of endeavor (e.g., sequencing power-on among plurality of processors ), Basile teaches a first power-on control circuitry (one of control state machine 214) associated with a first one or more processors (one of CPU 102) and a second power-on control circuitry (another one of control state machine 214) associated with a second one or more processors (another CPU 102) [Para: 0014(plurality of “agents 202 can include CPUs 102” or plurality of CPUs, 0009 where “Each of the CPUs 102 includes dedicated power control state machine 214”, see 0017 )]; and
wherein the first power-on control circuitry modulates the timing of when the first set of one or more processors powers on to differentiate from a timing of when at least some of the one or more second sets of one or more processors power on as controlled by the second power-on control circuitry [Para: 0016 (“power sequencer 212 implements a power-up sequence … selects one CPU at a time for power-up. After a given CPU has completed its power-up, the power sequencer 212 selects another CPU. In this manner, the CPUs 102 are powered-up sequentially and not all at the same time” when “a power control state machine 214 indicates that one of the CPUs 102 is to be powered-on” see 0018)].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Mar’s teachings of a connection to obtain power from a power supply to power a first set of one or more processors and the first power-on control circuitry, wherein the power supply is shared by one or more other electronic components having one or more second sets of one or more processors and the power-on control circuitry with Basile’s teachings of modulating a time by differentiating one processor power on to another processor power on when plurality of processors having respective power-on control circuit sharing same power supply which would allow Mar to dynamically powering on CPUs with respective power-on control circuitry to avoid voltage drop due to a sudden spike in current usage or inrush current (from all components powering up at the same time) which may corrupt data in memory.
Regarding Claims 2, 9 and 16, Mar teaches the power-on control circuitry of the electronic component to modulate the time when at least the portion of the electronic component including the first set of one or more processors are to power-up based on a random time generated for at least the portion of the electronic component to power-up [Para: 0011 (generated “programmable delay” can be any time that is suited for modulation or random time delay in order to sequential power-on of processors)].
Regarding Claims 3, 10 and 17, Mar teaches the random time generated for the first set of one or more processors to power-up comprise a random time within a limited time window [Para: 0011(as “waiting second programmable delay” before another control logic signal)].
Regarding Claims 4 and 11, Mar teaches the limited time window comprises a configurable limited time window [Para: 0011(programmable delay is configurable)].
Regarding Claims 5, 12 and 18, Mar teaches the electronic component to configure the configurable limited time window based on at least one of a power-up time of the first set of one or more processors [Para: 011(“programmable delay for the VRM to stabilize its voltage output lines to appropriate levels, the VRM asserts a VRM power_good signal to the VRM's processor” to power up processor as “multiple power good output lines … power supply controls the power-on sequencing for all processors”, see 0025)], a power-up time of one or more other processors of one or more other electronic components, or a total number of other electronic components receiving power from a same power source as the electronic component.
Regarding Claims 6, 13 and 19, Mar teaches the first power-on control circuitry to modulate the time when the one or more processors power on based on:
a request from the first power-on control circuitry to a main power-on control circuitry to request that the one or more processors power-up [Para: 0022(control logic 320 transmit power_good by “output terminals of the control logic 320 couple to the power_good input terminals power_good0, power_good1, power_good2 and power_goodn” to VRM 325)]; and
receipt, by the first power-on control circuitry, of a control signal from the main power-on control circuitry responsive to the request [Para: 0023(“VRM 325 receives a power_good input signal from the control logic”)].
Regarding Claims 7, 14 and 20, Mar teaches the first power-on control circuitry to modulate the time when the first set of one or more processors power on based on communication between the first power-on control circuitry (control logic 320) and at least one other electronic component (VRM 330), the communication to indicate a respective power on status for the at least one other electronic component [Para: 0023(as the communication of “Each VRM also generates a VRMP_G signal … that notifies the control logic 320 … appropriate voltage level” in order to power up processor)].
Response to Arguments
4. Applicant’s arguments with respect to claim(s) 1, 8 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED H REHMAN whose telephone number is (571)272-1412. The examiner can normally be reached 8.00 - 5.00.
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/MOHAMMED H REHMAN/Primary Examiner, Art Unit 2176
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