DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 2 (FIG. 11, claims 1-14) in the reply filed on 06/05/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-9, 11 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over KA et al, 20170294502.
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Regarding claim 1, fig. 3 of KA discloses a display panel comprising:
a first metal layer (layer on 130 such as SL1, 135 and DT1) on a first plane (plane of 130);
a second metal layer (layer within and on 140 – such as DT2 and DT3) on a second plane (plane of 140) different from the first plane; and
a third metal layer (layer on such as 170 and VDD2) on a third plane different from the first plane and the second plane,
wherein each of a plurality of first patterns (left DT1 and right DT1 in fig. 2) of the first metal layer is curved or bent along a hole surrounding area WA corresponding to a periphery of a hole FA in an active area,
wherein each of a plurality of second patterns (DT3 in fig. 2) of the second metal layer is curved or bent along the hole surrounding area,
wherein each of a plurality of third patterns (left half of VDD2 pattern and right half of VDD2 pattern in fig. 2) of the third metal layer is curved or bent along the hole surrounding area,
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wherein one of the plurality of first patterns, one of the plurality of second patterns and one of the plurality of third patterns overlap with each other in a thickness direction of the display panel in the hole surrounding area,
wherein the first metal layer comprises a gate line 135,
wherein the second metal layer comprises a storage electrode ([0095] a storage electrode including a storage capacitor Cst may be disposed between the second gate insulation layer 132 and an interlayer insulation layer 140) overlapping the first metal layer (note the second metal layer overlapping the first metal layer), and
wherein the third metal layer comprises a data line (170 is data line as well as VDD2 is a type of data line).
Regarding claim 2, fig. 3 of KA discloses wherein the first metal layer comprises a first gate line, wherein the second metal layer comprises a second gate line (as it is above the second insulating layer), and wherein the third metal layer comprises a source-drain pattern (170 is a type of source-drain pattern as it is connected to 155 and electrical a same pattern).
Regarding claim 3, KA discloses wherein the first gate line is configured to receive a first gate signal, and wherein the second gate line is configured to receive a second gate signal different from the first gate signal.
Regarding claim 7, fig. 2 of KA discloses wherein the one of the plurality of second patterns does not overlap other ones of the plurality of first patterns except for the one of the plurality of first patterns.
Regarding claim 8, fig. 2 of KA discloses wherein the one of the plurality of second patterns does not overlap other ones of the plurality of third patterns except for the one of the plurality of third patterns.
Regarding claim 9, fig. 10 of KA discloses further comprising a fourth metal layer 190 on a fourth plane different from the first plane, the second plane and the third plane, wherein each of a plurality of fourth patterns (left side pixel and right side pixel pattern) of the fourth metal layer is curved or bent along the hole surrounding area, and wherein the one of the plurality of first patterns, the one of the plurality of second patterns, the one of the plurality of third patterns and one of the plurality of fourth patterns overlap each other in the thickness direction of the display panel in the hole surrounding area (see fig. 10 and fig. 3 together).
Regarding claim 11, fig. 3 discloses wherein the first gate line does not overlap the second gate line in the thickness direction in a normal area, which is not the hole surrounding area.
Regarding claim 13, fig. 2 of KA discloses wherein the one of the plurality of first patterns, the one of the plurality of second patterns and the one of the plurality of third patterns that overlap each other have a same curvity (curvity which is a measure of curve can be zero and therefore of zero at the point of overlap – applicant did not specify curvity value) in a plan view in the hole surrounding area.
Regarding claim 14, fig. 10 of KA wherein the one of the plurality of first patterns, the one of the plurality of second patterns, the one of the plurality of third patterns and the one of the plurality of fourth patterns that overlap each other have a same curvity (curvity which is a measure of curve can be zero and therefore of zero at the point of overlap - applicant did not specify curvity value) in a plan view in the hole surrounding area (this is necessary the case).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 46 are rejected under 35 U.S.C. 103 as being unpatentable over KA in view of Choi et al. 20180212016.
Regarding claim 4, KA discloses claim 1, but does not disclose further comprising a pixel comprising a P-type transistor and an N-type transistor. However, fig. 1 and par [0041] The transistors T1, T2, T3, T4, T5, T6, and T7 may be P-type channel transistors such as a PMOS, however the present invention is not limited thereto, and at least one among the transistors T1, T2, T3, T4, T5, T6, and T7 may be an N-type channel transistor.
As such it would have been obvious to form a panel of KA further comprising a pixel comprising a P-type transistor and an N-type transistor such as taught by Choi as P-type transistor and an N-type transistor are building blocks of semiconductor devices.
Regarding claim 5, KA discloses wherein the first metal layer comprises a first gate line configured to transmit a first gate signal a transistor, and wherein the second metal layer comprises a second gate electrode of a transistor.
KA does not discloses that the transistor is the P-type transistor and does not disclose the second gate electrode is that of the P-type transistor or the N-type transistor.
However, fig. 1 and par [0041] The transistors T1, T2, T3, T4, T5, T6, and T7 may be P-type channel transistors such as a PMOS, however the present invention is not limited thereto, and at least one among the transistors T1, T2, T3, T4, T5, T6, and T7 may be an N-type channel transistor.
As such it would have been obvious to form a panel of KA further comprising wherein the transistor is the P-type transistor and the second gate electrode is that of the P-type transistor or the N-type transistor such as taught by Choi as P-type transistor and an N-type transistor are building blocks of semiconductor devices.
Regarding claim 6, KA discloses wherein the first metal layer comprises a first gate line configured to transmit a first gate signal a transistor, and wherein the second metal layer comprises a second gate line configured to transmit a second gate signal to a transistor.
KA does not discloses that the transistor is the P-type transistor and does not disclose wherein that the second gate line configured to transmit a second gate signal to the P-type transistor or the N-type transistor.
However, fig. 1 and par [0041] The transistors T1, T2, T3, T4, T5, T6, and T7 may be P-type channel transistors such as a PMOS, however the present invention is not limited thereto, and at least one among the transistors T1, T2, T3, T4, T5, T6, and T7 may be an N-type channel transistor.
As such it would have been obvious to form a panel of KA further comprising wherein the transistor is the P-type transistor and wherein the second gate line configured to transmit a second gate signal to the P-type transistor or the N-type transistor such as taught by Choi as P-type transistor and an N-type transistor are building blocks of semiconductor devices.
Allowable Subject Matter
Claims 10 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
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