Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Applicants’ response of 09/08/2026 has been entered in the record and considered. With respect to the rejection claims 35 USC 102 (a)(1) is withdrawn in view of applicants’ amendments. Applicants added new claims 21-34 are added.
New independent claims 21-25 are rejected. Claims 1-21 and newly added claims 26-34 are allowed as these claims include the limitations of the previously objected allowable claims. Claims 1-34 are under consideration. Claims 21-25 are rejected. Claims 1-20 and newly added claims 26-34 are allowed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2010/0320461 to Su et al. (SU) in view of US Pub # 2016/0343702 to Tomita et al. (Tomita).
Regarding independent claim 21, Su discloses a semiconductor device (Fig. 4H), comprising:
a semiconductor substrate (Fig. 4H: 402);
an active device region (see Examiner’s Mark-up below) comprising a plurality of gate trenches (403A and 403B) formed at a first main surface of the semiconductor substrate (402);
a current sensor region (see Examiner’s Mark-up below) comprising a plurality of gate trenches (405A and 405B) formed at the first main surface of the semiconductor substrate (402); and
a transition region (see Examiner’s Mark-up below) arranged between the active device region and the current sensor region,
wherein the transition region comprises a supplementary trench (406) formed at the first main surface of the semiconductor substrate (402),
wherein the supplementary trench (406) separates the plurality of gate trenches (403A and 403B) of the active device region from the plurality of gate trenches (405A and 405B) of the current sensor region,
wherein an electrode (408 and ¶0035) formed in the supplementary trench (406) is neither electrically connected (¶0037) to gate electrodes (408) formed in the plurality of gate trenches (403A and 403B) of the active device region nor electrically connected to gate electrodes (408) formed in the plurality of gate trenches (405A and 405B) of the current sensor region (see ¶0037), (¶0037 explicitly discloses “The P-type dopants 412 proximate the isolation trench 406 form body rings that help provide electrical isolation between the main FET and the sense FET”),
wherein the semiconductor device further comprises:
an emitter/source pad (Fig. 4H: 421) formed over the semiconductor substrate (402) and electrically connected to a source region (413 and ¶0037) formed in the active device region;
a sense pad (Fig. 4H: 422) formed over the semiconductor substrate and electrically connected to a source region (414) formed in the current sensor region; and
a gate pad (Fig. 4H: 420) formed over the semiconductor substrate and electrically connected to the gate electrodes (408) of the active device region and to the gate electrodes (408) of the current sensor region (see ¶0038 and Fig. 4G).
Su does not expressly disclose:
a temperature sensor region comprising a temperature sensor device, wherein a first terminal of the temperature sensor device is electrically connected to the sense pad.
However, Tomita teaches a temperature sensor region (94) comprising a temperature sensor device (including first sense electrode 51, second sense electrode 52, and temperature-dependent resistance layer 50),
wherein a first terminal (first sense electrode 51) of the temperature sensor device provides an electrical connection for temperature sensing (see Figs. 1 and 6 and ¶0037, 0043 -0044 of Tomita).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the temperature sensor region (94) of Tomita into the semiconductor device of Su to monitor temperature conditions affecting the current-sensing performance of the semiconductor device.
In the proposed modification, the first terminal (51) of Tomita’s temperature sensor device would be electrically connected to the existing sense pad (422) of Su, thereby providing a common sensing terminal for the current sensor and the temperature sensor.
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Allowable Subject Matter
Claims 1-20 and 26-34 are allowed.
Amended independent claim 1 and newly added independent claims 26 and 27 are allowed because these claims have been amended to incorporate the previously dependent claims 3, 11 and 13, respectively.
The examiner’s reasons for independent claims 1 and newly added independent claims, 26 and 27 and their respective dependent claims are of record in June 17, 2026 Office action.
Claims 22-25 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 22 recites:
“wherein the semiconductor device is configured to allow for a measurement of a current in the current sensor region using the sense pad when the gate pad is switched to a first state, and wherein the semiconductor device is further configured to allow for a measurement of a temperature of the semiconductor device using the sense pad when the gate pad is switched to a second state.”
Claim 24 recites:
“wherein a second terminal of the temperature sensor device is electrically connected to the emitter/source pad.”
Claim 25 recites:
“wherein the temperature sensor device comprises a plurality of diodes coupled in series.”
Response to Arguments
Applicant’s response filed September 8, 2026, has been entered and considered.
The rejection of claims 1 and 2 under 35 U.S.C. 102(a)(1) is withdrawn in view of Applicant’s amendments.
Amended independent claim 1 is allowable because the claim, including the limitation incorporated from former claim 3, has been determined to define patentable subject matter.
Claims 1-20 and 26-34 are allowed. Claims 21-25 remain rejected under 35 U.S.C. 103 for the reasons set forth below.
Applicant’s arguments regarding independent claim 21 have been considered.
Applicant argues that Tomita does not disclose a terminal of the temperature sensor device electrically connected to the same sense pad associated with the current sensor region of Su.
The Examiner respectfully disagrees to the extent that Applicant’s argument addresses only the individual disclosures of the references rather than the proposed combination under 35 U.S.C. 103.
Specifically, Su teaches a sense pad (422) electrically connected to the source region (414) of the current sensor region (Fig. 4H). Tomita teaches a temperature sensor region (94) comprising a temperature sensor device having first and second sense electrodes (51, 52), wherein the temperature is detected based on temperature-dependent electrical characteristics (Figs. 1 and 6; ¶0037 and 0043-0044).
The proposed combination provides for electrically connecting the first sense electrode (51) of Tomita to the existing sense pad (422) of Su, such that the sense pad (422) serves as a common electrical connection for the current sensor region and the temperature sensor device.
Accordingly, the rejection does not rely on Tomita individually disclosing the sense pad (422) of Su, but rather on the proposed combination of the teachings of Su and Tomita under 35 U.S.C. 103.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub # 2020/0335622 to Hiyoshi, US Pub # 2018/0277641 to Karmous, US Pub # 2017/0179278 to Baldwin et al., US Pub # 2024/0014300 to Osawa.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MOHSEN AHMADI/ Primary Examiner, Art Unit 2896
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