DETAILED ACTION 1000-1
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/29/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Chang et al. (US 2009/0278196 A1).
4. Regarding claim 1, Chang et al. teach in Figs. 33-34, a semiconductor device (the second embodiment of the planar transistor and the FinFET; [0022-0023]) comprising: a first device (the planar transistor; [0022-0023]) including a first fin structure (100; [0032]) on a substrate (30; [0029]), a first gate dielectric layer (the bottom layer of 112; [0040]) on the first fin structure (100) and a first gate electrode (the top layer of 112; [0040]) on the first gate dielectric layer (the bottom layer of 112); and a second device (the FinFET; [0022-0023]) including a second fin structure (the bottom portion of 200; [0036]) on the substrate (30), an oxide layer (52s; [0036]) disposed over the second fin structure (the bottom portion of 200), a channel semiconductor layer (the upper portion of 200; [0036]) disposed on the oxide layer (52s), a second gate dielectric layer (the bottom layer of 212; [0040]) on the channel semiconductor layer (the upper portion of 200), and a second gate electrode (the upper layer of 212; [0040]) on the second gate dielectric layer (the bottom layer of 212), wherein the first gate dielectric layer (the bottom layer of 112) is directly formed on a top of the first fin structure (100; see Fig. 34, [0040]), and the oxide layer (52s) separates the channel semiconductor layer (the upper portion of 200) from the second fin structure (the bottom portion of 200; see Fig. 33).
5. Regarding claim 2, Chang et al. teach in Figs. 33-34, the semiconductor device of claim 1, wherein the top of the first fin structure (100) has a convex shape (see the top corners of 100 in Fig. 33).
6. Regarding claim 3, Chang et al. teach in Figs. 33-34, the semiconductor device of claim 1, wherein the oxide layer (52s) includes silicon and germanium (oxidation of a portion of 200 in Fig. 28 [0043]; and 200 is a portion of the 30 in Figs. 7, [0032]; and 30 can be a silicon substrate including germanium; [0029]).
7. Regarding claim 4, Chang et al. teach in Figs. 33-34, the semiconductor device of claim 1, further comprising an isolation dielectric layer (56, 52’ and 40; [0032, 0037, 0043]).
8. Regarding claim 5, Chang et al. teach in Figs. 33-34, the semiconductor device of claim 4, wherein the first fin structure (100) and the second fin structure (the bottom portion of 200) are embedded in the isolation dielectric layer (56, 52’ and 40).
9. Regarding claim 6, Chang et al. teach in Figs. 33-34, the semiconductor device of claim 5, wherein a top of the first fin structure (the top horizontal surface of 100) and an upper surface of the oxide layer (the upper surface of 52s) are located below an upper surface of the isolation dielectric layer (the top surface of 56, 52’ and 40; see Fig. 33).
10. Regarding claim 7, Chang et al. teach in Figs. 33-34, the semiconductor device of claim 1, wherein the first gate dielectric layer (the bottom layer of 112) is disposed on at least a bottom face of the first gate electrode (the top layer of 112; see Fig. 34).
11. Regarding claim 8, Chang et al. teach in Figs. 33-34, the semiconductor device of claim 7, wherein the first gate dielectric layer (the bottom layer of 112) is disposed on side faces (bottom side faces) of the first gate electrode (the top layer of 112; see Fig. 34).
Allowable Subject Matter
Claims 9-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or suggest, singularly or in combination, at least the limitations of "wherein the first gate dielectric layer is directly formed on a curved top surface of the first fin" as recited in claim 9, and “wherein an uppermost surface of the dielectric layer is disposed above a bottommost surface of the first gate electrode, wherein the first u-shaped gate dielectric layer is directly formed on a curved top surface of the first fin” as recited in claim 15.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zhu et al. (US 2015/0270263 A1) teach a semiconductor device having two FinFETs having body spacers in the fin structure.
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/HSIN YI HSIEH/Primary Examiner, Art Unit 2899 7/8/2026
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