Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Applicants’ response of 08/27/2026 has been entered in the record and considered. With respect to the rejections under 35 USC 102 (a)(1) and the rejections under 35 USC 103 (a) the Applicant’s arguments have been considered but they are not persuasive for the reasons discussed below. Claims 1-20 are under consideration. Claims 1-20 are rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP5899803 to Nobuo et al (cited in IDS).
Regarding independent claim 1, Nobuo a semiconductor component (Figs. 6-8 and ¶0012-0016, 0041-0056), comprising:
a substrate (10);
a channel layer (21) and a barrier layer (22), sequentially stacked on the substrate;
a source (3) and a drain (4), disposed on the barrier layer;
a first gate (5) and a second gate (6), disposed on the barrier layer and located between the source and the drain, wherein the second gate (6) is disposed between the first gate (5) and the drain (4);
a first gate field plate (50), at least partially disposed on a first gate side (5) close to the drain (4); and
a first source field plate (30) covering the first gate field plate (50),
wherein the first source field plate (Fig. 6: 30) is electrically connected to the source (Fig. 6: 3).
Regarding claim 2, Nobuo discloses a second gate field plate at least partially located on a second gate side close to the drain (Fig. 6: 60 and ¶0042).
Regarding claim 3, Nobuo discloses a second source field plate covering the second gate field plate. Note that the term "first" and "second" source field plate imply a connection to the same i.e. source potential and hence, an electrical connection of some sort must exist between the two field plates. Therefore, the subject- matter of claim 3 is considered disclosed by the single field plate of (Fig. 6: 30). Additionally, the division of a single source field-plate into two separate field-plates is a well known field-plate design option.
Regarding claim 4, Nobuo discloses wherein the first source field plate covers the second gate field plate (Fig. 6, wherein the source field plate (30) covers the second gate field plate (60).
Regarding claim 5, Nobuo discloses wherein the first source field plate is connected to the second source field plate (Fig. 6, wherein source field plate (30) covers both gate field plates ref. 50 and (60).
Regarding claim 6, Nobuo discloses wherein a spacing between the first gate field plate and the second gate is within a range from 0.5 µm to 2.7 µm (Figs. 6 and 8 and ¶0045, where the distance L_GZ -L_GFP = 2um falls within the claimed range. It should however, be noted, that the claimed values are common distances of electrode-electrode spacing in HEMTs and hence, can be provided without an inventive step by the skilled person).
Regarding claim 7, Nobuo discloses wherein the first gate field plate comprises a first part disposed on the first gate side close to the drain and a second part disposed on a first gate side close to the source, and the first part and the second part are separately in contact with and connected to the first gate (Fig. 6: 50 and ¶0017).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8- 20 are rejected under 35 U.S.C. 103 as being unpatentable over JP Pub # 5899803 to Nobuo et al. (Nobuo) in view of JP Pub # 2007073815 to Yoshitomo et al. (Yoshitomo, cited in IDS).
Regarding claim 8, Nobuo discloses all of the limitations of claim 1 from which this claim depends. Nobuo discloses the second gate and the drain.
Nobuo fails to explicitly disclose a third gate disposed between the second gate and the drain.
Yoshitomo discloses a third gate disposed between the second gate and the drain (Fig. 5: 109 and ¶0026-0027).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the second gate and the drain with the third gate as taught by Yoshitomo in order to improve the distortion characteristics of the high-frequency switch circuit without causing an increase in device area or an increase in manufacturing cost based thereon (see Yoshitomo).
Regarding claim 9, Nobuo discloses all of the limitations of claim 8 from which this claim depends.
Nobuo fails to explicitly disclose a third gate field plate at least partially disposed on a third gate side close to the drain.
Yoshitomo discloses a third gate field plate (107) at least partially disposed on a third gate side (base portion of 107) close to the drain (wherein again, references is made to the T-shaped electrode).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the semiconductor component of Nobuo with the third gate field plate as taught by Yoshitomo in order to improve the distortion characteristics of the high-frequency switch circuit without causing an increase in device area or an increase in manufacturing cost based thereon (see Yoshitomo).
Regarding claim 10, Nobuo discloses all of the limitations of claim 9 from which this claim depends.
Nobuo fails to explicitly disclose a third source field plate that covers the third gate field plate.
Yoshitomo discloses a third source field plate (Fig. 6: 110) that covers the third gate field plate (107).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the third gate field plate of Nobuo with the third source field plate as taught by Yoshitomo in order to improve the distortion characteristics of the high-frequency switch circuit without causing an increase in device area or an increase in manufacturing cost based thereon (see Yoshitomo).
Regarding independent claim 11, Nobuo discloses an electronic device (Figs. 6-8 and ¶0012-0016, 0041-0056), comprising:
a semiconductor component (Figs. 6-8), and
wherein the semiconductor component (Figs. 6-8) comprises:
Nobuo a semiconductor component (Figs. 6-8 and ¶0012-0016, 0041-0056), comprising:
a substrate (10);
a channel layer (21) and a barrier layer (22), sequentially stacked on the substrate;
a source (3) and a drain (4), disposed on the barrier layer;
a first gate (5) and a second gate (6), disposed on the barrier layer and located between the source and the drain, wherein the second gate (6) is disposed between the first gate (5) and the drain (4);
a first gate field plate (50), at least partially disposed on a first gate side (5) close to the drain (4); and
a first source field plate (30) covering the first gate field plate (50),
wherein the first source field plate (Fig. 6: 30) is electrically connected to the source (Fig. 6: 3).
Nobuo fails to explicitly disclose an antenna, wherein the semiconductor component is configured to amplify a radio frequency signal and output the amplified radio frequency signal to the antenna for radiation.
Yoshitomo discloses an antenna, wherein the semiconductor component is configured to amplify a radio frequency signal and output the amplified radio frequency signal to the antenna for radiation (¶0002-0003).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the electronic device of Nobuo with the antenna as taught by Yoshitomo so that the switching element has a small insertion loss and does not require a DC bias current unlike a diode (see Nobuo).
Regarding independent claim 12, Nobuo discloses an electronic device (Figs. 6-8 and ¶0012-0016, 0041-0056), comprising:
a semiconductor component (Figs. 6-8), and
wherein the semiconductor component (Figs. 6-8) comprises:
a conductive substrate (10); (The Examiner finds that the silicon carbide substrate disclosed by Nobuo reasonably corresponds to the claimed conductive substrate because silicon carbide is a semiconductor material capable of electrical conduction and is conventionally used in conductive substrate implementations.)
a channel layer (21) and a barrier layer (22), sequentially stacked on the substrate;
a source (3) and a drain (4), disposed on the barrier layer;
a first gate (5) and a second gate (6), disposed on the barrier layer and located between the source and the drain, wherein the second gate (6) is disposed between the first gate (5) and the drain (4);
a first gate field plate (50), at least partially disposed on a first gate side (5) close to the drain (4); and
a first source field plate (30) covering the first gate field plate (50),
wherein the first source field plate (Fig. 6: 30) is electrically connected to the source (Fig. 6: 3).
Nobuo fails to disclose a printed circuit board electrically connected to the semiconductor component.
Yoshitomo teaches that a high-performance FET is used for a high-frequency switch circuit provided between an antenna and a transmission circuit or between the antenna and a reception circuit (¶0002-0003).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Nobuo to incorporate the antenna arrangement of Yoshitomo because doing so would permit transmission and radiation of the amplified radio frequency signal using known RF integration techniques. As modified, the printed circuit board supporting or implementing the antenna would be electrically connected to the semiconductor component and therefore satisfy the claimed limitation reciting “a printed circuit board electrically connected to the semiconductor component.”
Regarding claim 13, Nobuo discloses a second gate field plate at least partially located on a second gate side close to the drain (Fig. 6: 60 and ¶0042).
Regarding claim 14, Nobuo discloses a second source field plate covering the second gate field plate. Note that the term "first" and "second" source field plate imply a connection to the same i.e. source potential and hence, an electrical connection of some sort must exist between the two field plates. Therefore, the subject- matter of claim 3 is considered disclosed by the single field plate of (Fig. 6: 30). Additionally, the division of a single source field-plate into two separate field-plates is a well-known field-plate design option.
Regarding claim 15, Nobuo discloses wherein the first source field plate covers the second gate field plate (Fig. 6, wherein the source field plate (30) covers the second gate field plate (60).
Regarding claim 16, Nobuo discloses wherein the first source field plate is connected to the second source field plate (Fig. 6, wherein source field plate (30) covers both gate field plates ref. 50 and (60).
Regarding claim 17, Nobuo discloses wherein a spacing between the first gate field plate and the second gate is within a range from 0.5 µm to 2.7 µm (Figs. 6 and 8 and ¶0045, where the distance L_GZ -L_GFP = 2um falls within the claimed range. It should however, be noted that the claimed values are common distances of electrode-electrode spacing in HEMTs and hence, can be provided without an inventive step by the skilled person).
Regarding claim 18, Nobuo discloses wherein the first gate field plate comprises a first part disposed on the first gate side close to the drain and a second part disposed on a first gate side close to the source, and the first part and the second part are separately in contact with and connected to the first gate (Fig. 6: 50 and ¶0017).
Regarding claim 19, Nobuo discloses all of the limitations of claim 12 from which this claim depends. Nobuo discloses the second gate and the drain.
Nobuo fails to explicitly disclose a third gate disposed between the second gate and the drain.
Yoshitomo discloses a third gate disposed between the second gate and the drain (Fig. 5: 109 and ¶0026-0027).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the second gate and the drain with the third gate as taught by Yoshitomo in order to improve the distortion characteristics of the high-frequency switch circuit without causing an increase in device area or an increase in manufacturing cost based thereon (see Yoshitomo).
Regarding claim 20, Nobuo discloses all of the limitations of claim 19 from which this claim depends.
Nobuo fails to explicitly disclose a third gate field plate at least partially disposed on a third gate side close to the drain a third source field plate that covers the third gate field plate.
Yoshitomo discloses a third gate field plate (107) at least partially disposed on a third gate side (base portion of 107) close to the drain (wherein again, references is made to the T-shaped electrode) a third source field plate (Fig. 6: 110) that covers the third gate field plate (107).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the semiconductor component of Nobuo with the third gate field plate as taught by Yoshitomo in order to improve the distortion characteristics of the high-frequency switch circuit without causing an increase in device area or an increase in manufacturing cost based thereon (see Yoshitomo).
Response to Arguments
Applicant's arguments filed 08/27/2026 have been fully considered but they are not persuasive.
Regarding independent Claim 1:
Applicant argues that Nobuo fails to disclose the claimed first source field plate electrically connected to the source and further asserts that the claimed arrangement provides improved electrical characteristics.
However, Nobuo discloses a first source field plate (30) covering the first gate field plate (50), wherein the first source field plate (30) is electrically connected to the source electrode (3) through source electrode wiring (31), as illustrated in Fig. 6 and described in the corresponding specification.
Thus, Nobuo expressly discloses the newly added limitation requiring the first source field plate to be electrically connected to the source.
Furthermore, the claimed functional advantages, including reduced parasitic capacitance, increased breakdown voltage, and improved small-signal gain, do not distinguish the claimed invention from Nobuo because independent claim 1 does not expressly require these performance characteristics.
The Examiner maintains that Nobuo discloses the claimed structural arrangement, including the newly added electrical connection, as set forth in the rejection under 35 U.S.C. 102(a)(1).
Accordingly, Applicant’s arguments do not overcome the rejection of independent claim 1.
Regarding Dependent Claim 3:
Applicant’s arguments concerning claim 3 have been considered.
Applicant argues that Nobuo discloses a single continuous source field plate rather than first and second source field plates.
The Examiner notes that the determination of anticipation is based on the structural limitations recited in the claim, rather than whether the prior art assigns separate names to the corresponding portions of a conductive structure.
To the extent that separately identifiable portions of Nobuo’s structure satisfy the claimed first and second source field plates, the fact that such portions are electrically continuous does not, by itself, preclude the claimed arrangement.
Accordingly, the applicability of Nobuo to claim 3 is based on the structural configuration and relationships of the identified portions as shown in the cited figures.
Regarding Dependent Claim 6:
Applicant’s arguments regarding claim 6 have been considered but are not persuasive.
Applicant argues that Nobuo does not disclose the entire claimed spacing range of 0.5 µm to 2.7 µm and that the selected range provides improved performance and reliability.
However, Nobuo discloses a spacing of 2 µm, which falls within the claimed range of 0.5 µm to 2.7 µm.
The Examiner notes that anticipation does not require the prior art to disclose every value within the claimed range. Rather, the disclosure of a specific value falling within the claimed range is sufficient to satisfy the numerical limitation.
Accordingly, because Nobuo expressly discloses a spacing of 2 µm within the claimed range, Applicant’s argument does not distinguish claim 6 from the cited prior art, and the rejection under 35 U.S.C. 102(a)(1) is maintained.
Regarding Dependent Claim 7:
Applicant’s arguments regarding claim 7 have been considered.
Applicant argues that the claimed first and second parts of the first gate field plate provide improved alignment tolerance and avoid adverse effects on the width of the first gate.
The Examiner notes that claim 7 is directed to a structural arrangement rather than a particular manufacturing method or a specified degree of alignment precision.
Accordingly, the alleged technical advantages do not independently distinguish the claim where the corresponding structural limitations are disclosed in Nobuo.
The determination of anticipation depends on whether Nobuo discloses the first and second parts of the gate field plate in the positional and electrical relationships recited in claim 7.
Regarding the Combination of Nobuo and Yoshitomo:
Applicant’s arguments regarding the proposed combination of Nobuo and Yoshitomo have been considered.
Applicant argues that the references address different technical problems and that their combination would be based on improper hindsight.
The Examiner notes that references need not address identical technical problems to be properly combined under 35 U.S.C. 103. The determination of obviousness considers the teachings of the references as a whole and whether a person of ordinary skill in the art would have had a reason to combine their teachings with a reasonable expectation of success.
Nobuo discloses a semiconductor component having multiple gate electrodes and field plates, while Yoshitomo discloses semiconductor field-effect transistors employed in high-frequency signal applications.
The fact that Yoshitomo describes a high-frequency switching application does not, by itself, prevent its teachings from being considered in connection with Nobuo’s semiconductor structure.
Regarding Reasonable Expectation of Success:
Applicant’s arguments regarding the alleged lack of a reasonable expectation of success have been considered.
Applicant argues that combining the gate structures of Nobuo and Yoshitomo would introduce additional complexity and unpredictable interactions among the gate electrodes and field plates.
The Examiner notes that the possibility of increased structural complexity does not, by itself, establish that a person of ordinary skill in the art would lack a reasonable expectation of success.
Both references concern semiconductor devices incorporating multiple gate electrodes, and the determination of obviousness must consider whether the proposed modification would have been technically achievable using the teachings of the cited references and the knowledge of one of ordinary skill in the art.
The Examiner has considered Applicant’s arguments concerning the interaction between the gate structures and the asserted technical advantages of the claimed arrangement.
Regarding Independent Claim 11:
Applicant’s arguments regarding independent claim 11 have been considered.
Applicant argues that Yoshitomo is directed to a high-frequency switching circuit rather than a power amplifier and therefore does not provide a sufficient basis for combining its teachings with Nobuo.
The Examiner notes that Yoshitomo discloses the use of semiconductor field-effect transistor devices in high-frequency signal applications involving an antenna.
Although the references describe different circuit applications, this difference does not automatically render the combination improper under 35 U.S.C. 103.
Nevertheless, the claimed limitation requiring the semiconductor component to amplify a radio-frequency signal and output the amplified signal to the antenna must be addressed by the teachings of the cited references and the proposed modification.
Regarding Independent Claim 12:
Applicant’s arguments regarding independent claim 12 have been considered.
Applicant argues that a silicon carbide substrate may be either conductive or semi-insulating and therefore Nobuo’s disclosure of a silicon carbide substrate does not necessarily establish the claimed conductive substrate.
The Examiner acknowledges that silicon carbide substrates can have different electrical properties depending on their composition and doping characteristics.
Accordingly, the claimed conductive substrate must be evaluated based on the particular teachings of Nobuo concerning substrate (10), rather than relying solely on the general identification of silicon carbide as a semiconductor material.
Applicant further argues that the claimed connection to a printed circuit board represents a deliberate design choice. However, a difference in the stated design objective does not, by itself, establish patentability under 35 U.S.C. 103 where the claimed arrangement would have been obvious from the teachings of the cited references.
Regarding Dependent Claims 13-20:
Applicant’s arguments regarding dependent claims 13-20 have been considered.
Applicant argues that claims 13-20 are patentable by virtue of their dependency from independent claim 12 and further relies on the arguments previously presented concerning the corresponding limitations of claims 2-10.
The Examiner notes that the patentability of dependent claims 13-20 must be evaluated based on all limitations of the respective claims, including the limitations incorporated through their dependency.
To the extent that Applicant repeats arguments previously addressed, the Examiner refers to the corresponding responses set forth above. The additional limitations of dependent claims 13-20 are addressed separately in the applicable rejections under 35 U.S.C. 103.
Regarding Applicant’s Alleged Unexpected Results
Applicant’s arguments regarding the alleged unexpected results presented in Tables 1 and 2 of the specification have been considered.
Applicant asserts that the claimed dual-gate configuration provides a reduction in knee-point voltage, an increase in small-signal gain, and a reduction in gate-drain parasitic capacitance.
However, the Examiner notes that the reported results compare different configurations presented in Applicant’s specification and do not establish that the claimed invention provides unexpected results relative to the closest prior art, Nobuo.
While Tables 1 and 2 indicate improvements in certain electrical characteristics, Applicant has not adequately explained why such improvements would have been unexpected to one of ordinary skill in the art in view of the teachings of the cited prior art.
Furthermore, Applicant has not sufficiently established that the reported improvements are attributable to the particular distinguishing claim limitations, rather than to other differences between the compared device configurations.
Accordingly, the reported simulation results have been considered but are insufficient, on the present record, to establish unexpected results that overcome an otherwise properly supported prima facie case of obviousness. See MPEP § 716.02.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub # 2016/0322351 to Moens et al. JP Pub # 2010109322 to Fuji Electric system Co LTD.
Moens discloses (fig. 3, par. 31-43) which discloses a semiconductor component, comprising: a substrate (fig. 3, ref. 200, par. 31); a channel layer and a barrier layer, sequentially stacked on the substrate (fig. 3, ref. 244, 246, par. 32); a source and a drain, disposed on the barrier layer (fig. 3, ref. 272, 274, par. 38); a first gate (fig. 3, ref. 276, par. 38) and a second gate (fig. 3, ref. 277, par. 38), disposed on the barrier layer and located between the source and the drain, wherein the second gate is disposed between the first gate and the drain (fig. 3, ref. 277); a first gate field plate, at least partially disposed on a side that is of the first gate and that is close to the drain (fig. 3, ref. 276, noting par. 39 "each of gate electrodes 276 and 277 has a stepped structure where the portion closest to the channel film 244 is the gate for the transistor, and portions at higher elevations and extending laterally provide shielding help to reduce gate capacitance"); and a first source field plate, wherein the first source field plate covers the first gate field plate, and the first source field plate overlaps the first gate and does not cover the first gate (fig. 3, where reference is made only to field plate portion in the lowest wiring level ref. 2821, par. 42, "The shielding structure 282, including the portions 2821 and 2822, is electrically connected to the drain/source electrode 272". Note also that portion ref. 2822 is located at a different wiring level and thus regarded as an additional field plate), or the first source field plate does not overlap the first gate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHSEN AHMADI whose telephone number is (571)272-5062. The examiner can normally be reached M-F: 9:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHSEN AHMADI/Primary Examiner, Art Unit 2896
