Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/676,612 filed on May 29, 2024.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP5899803 to Nobuo et al (cited in IDS).
Regarding independent claim 1, Nobuo a semiconductor component (Figs. 6-8 and ¶0012-0016, 0041-0056), comprising:
a substrate (10);
a channel layer (21) and a barrier layer (22), sequentially stacked on the substrate;
a source (3) and a drain (4), disposed on the barrier layer;
a first gate (5) and a second gate (6), disposed on the barrier layer and located between the source and the drain, wherein the second gate (6) is disposed between the first gate (5) and the drain (4);
a first gate field plate (50), at least partially disposed on a first gate side (5) close to the drain (4); and
a first source field plate (30) covering the first gate field plate (50).
Regarding claim 2, Nobuo discloses a second gate field plate at least partially located on a second gate side close to the drain (Fig. 6: 60 and ¶0042).
Regarding claim 3, Nobuo discloses a second source field plate covering the second gate field plate. Note that the term "first" and "second" source field plate imply a connection to the same i.e. source potential and hence, an electrical connection of some sort must exist between the two field plates. Therefore, the subject- matter of claim 3 is considered disclosed by the single field plate of (Fig. 6: 30). Additionally, the division of a single source field-plate into two separate field-plates is a well known field-plate design option.
Regarding claim 4, Nobuo discloses wherein the first source field plate covers the second gate field plate (Fig. 6, wherein the source field plate (30) covers the second gate field plate (60).
Regarding claim 5, Nobuo discloses wherein the first source field plate is connected to the second source field plate (Fig. 6, wherein source field plate (30) covers both gate field plates ref. 50 and (60).
Regarding claim 6, Nobuo discloses wherein a spacing between the first gate field plate and the second gate is within a range from 0.5 µm to 2.7 µm (Figs. 6 and 8 and ¶0045, where the distance L_GZ -L_GFP = 2um falls within the claimed range. It should however, be noted, that the claimed values are common distances of electrode-electrode spacing in HEMTs and hence, can be provided without an inventive step by the skilled person).
Regarding claim 7, Nobuo discloses wherein the first gate field plate comprises a first part disposed on the first gate side close to the drain and a second part disposed on a first gate side close to the source, and the first part and the second part are separately in contact with and connected to the first gate (Fig. 6: 50 and ¶0017).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8- 20 are rejected under 35 U.S.C. 103 as being unpatentable over JP Pub # 5899803 to Nobuo et al. (Nobuo) in view of JP Pub # 2007073815 to Yoshitomo et al. (Yoshitomo, cited in IDS).
Regarding claim 8, Nobuo disclose all of the limitations of claim 1 from which this claim depends. Nobuo discloses the second gate and the drain.
Nobuo fails to explicitly disclose a third gate disposed between the second gate and the drain.
Yoshitomo discloses a third gate disposed between the second gate and the drain (Fig. 5: 109 and ¶0026-0027).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the second gate and the drain with the third gate as taught by Yoshitomo in order to improve the distortion characteristics of the high-frequency switch circuit without causing an increase in device area or an increase in manufacturing cost based thereon (see Yoshitomo).
Regarding claim 9, Nobuo disclose all of the limitations of claim 8 from which this claim depends.
Nobuo fails to explicitly disclose a third gate field plate at least partially disposed on a third gate side close to the drain.
Yoshitomo discloses a third gate field plate (107) at least partially disposed on a third gate side (base portion of 107) close to the drain (wherein again, references is made to the T-shaped electrode).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the semiconductor component of Nobuo with the third gate field plate as taught by Yoshitomo in order to improve the distortion characteristics of the high-frequency switch circuit without causing an increase in device area or an increase in manufacturing cost based thereon (see Yoshitomo).
Regarding claim 10, Nobuo disclose all of the limitations of claim 9 from which this claim depends.
Nobuo fails to explicitly disclose a third source field plate that covers the third gate field plate.
Yoshitomo discloses a third source field plate (Fig. 6: 110) that covers the third gate field plate (107).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the third gate field plate of Nobuo with the third source field plate as taught by Yoshitomo in order to improve the distortion characteristics of the high-frequency switch circuit without causing an increase in device area or an increase in manufacturing cost based thereon (see Yoshitomo).
Regarding independent claim 11, Nobuo discloses an electronic device (Figs. 6-8 and ¶0012-0016, 0041-0056), comprising:
a semiconductor component (Figs. 6-8), and
wherein the semiconductor component (Figs. 6-8) comprises:
Nobuo a semiconductor component (Figs. 6-8 and ¶0012-0016, 0041-0056), comprising:
a substrate (10);
a channel layer (21) and a barrier layer (22), sequentially stacked on the substrate;
a source (3) and a drain (4), disposed on the barrier layer;
a first gate (5) and a second gate (6), disposed on the barrier layer and located between the source and the drain, wherein the second gate (6) is disposed between the first gate (5) and the drain (4);
a first gate field plate (50), at least partially disposed on a first gate side (5) close to the drain (4); and
a first source field plate (30) covering the first gate field plate (50).
Nobuo fails to explicitly disclose an antenna, wherein the semiconductor component is configured to amplify a radio frequency signal and output the amplified radio frequency signal to the antenna for radiation.
Yoshitomo discloses an antenna, wherein the semiconductor component is configured to amplify a radio frequency signal and output the amplified radio frequency signal to the antenna for radiation (¶0002-0003).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the electronic device of Nobuo with the antenna as taught by Yoshitomo so that the switching element has a small insertion loss and does not require a DC bias current unlike a diode (see Nobuo).
Regarding independent claim 12, Nobuo discloses an electronic device (Figs. 6-8 and ¶0012-0016, 0041-0056), comprising:
a semiconductor component (Figs. 6-8), and
wherein the semiconductor component (Figs. 6-8) comprises:
a conductive substrate (10); (The Examiner finds that the silicon carbide substrate disclosed by Nobuo reasonably corresponds to the claimed conductive substrate because silicon carbide is a semiconductor material capable of electrical conduction and is conventionally used in conductive substrate implementations.)
a channel layer (21) and a barrier layer (22), sequentially stacked on the substrate;
a source (3) and a drain (4), disposed on the barrier layer;
a first gate (5) and a second gate (6), disposed on the barrier layer and located between the source and the drain, wherein the second gate (6) is disposed between the first gate (5) and the drain (4);
a first gate field plate (50), at least partially disposed on a first gate side (5) close to the drain (4); and
a first source field plate (30) covering the first gate field plate (50).
Nobuo fails to disclose a printed circuit board electrically connected to the semiconductor component.
Yoshitomo teaches that a high-performance FET is used for a high-frequency switch circuit provided between an antenna and a transmission circuit or between the antenna and a reception circuit (¶0002-0003).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Nobuo to incorporate the antenna arrangement of Yoshitomo because doing so would permit transmission and radiation of the amplified radio frequency signal using known RF integration techniques. As modified, the printed circuit board supporting or implementing the antenna would be electrically connected to the semiconductor component and therefore satisfy the claimed limitation reciting “a printed circuit board electrically connected to the semiconductor component.”
Regarding claim 13, Nobuo discloses a second gate field plate at least partially located on a second gate side close to the drain (Fig. 6: 60 and ¶0042).
Regarding claim 14, Nobuo discloses a second source field plate covering the second gate field plate. Note that the term "first" and "second" source field plate imply a connection to the same i.e. source potential and hence, an electrical connection of some sort must exist between the two field plates. Therefore, the subject- matter of claim 3 is considered disclosed by the single field plate of (Fig. 6: 30). Additionally, the division of a single source field-plate into two separate field-plates is a well known field-plate design option.
Regarding claim 15, Nobuo discloses wherein the first source field plate covers the second gate field plate (Fig. 6, wherein the source field plate (30) covers the second gate field plate (60).
Regarding claim 16, Nobuo discloses wherein the first source field plate is connected to the second source field plate (Fig. 6, wherein source field plate (30) covers both gate field plates ref. 50 and (60).
Regarding claim 17, Nobuo discloses wherein a spacing between the first gate field plate and the second gate is within a range from 0.5 µm to 2.7 µm (Figs. 6 and 8 and ¶0045, where the distance L_GZ -L_GFP = 2um falls within the claimed range. It should however, be noted, that the claimed values are common distances of electrode-electrode spacing in HEMTs and hence, can be provided without an inventive step by the skilled person).
Regarding claim 18, Nobuo discloses wherein the first gate field plate comprises a first part disposed on the first gate side close to the drain and a second part disposed on a first gate side close to the source, and the first part and the second part are separately in contact with and connected to the first gate (Fig. 6: 50 and ¶0017).
Regarding claim 19, Nobuo disclose all of the limitations of claim 12 from which this claim depends. Nobuo discloses the second gate and the drain.
Nobuo fails to explicitly disclose a third gate disposed between the second gate and the drain.
Yoshitomo discloses a third gate disposed between the second gate and the drain (Fig. 5: 109 and ¶0026-0027).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the second gate and the drain with the third gate as taught by Yoshitomo in order to improve the distortion characteristics of the high-frequency switch circuit without causing an increase in device area or an increase in manufacturing cost based thereon (see Yoshitomo).
Regarding claim 20, Nobuo disclose all of the limitations of claim 19 from which this claim depends.
Nobuo fails to explicitly disclose a third gate field plate at least partially disposed on a third gate side close to the drain a third source field plate that covers the third gate field plate.
Yoshitomo discloses a third gate field plate (107) at least partially disposed on a third gate side (base portion of 107) close to the drain (wherein again, references is made to the T-shaped electrode) a third source field plate (Fig. 6: 110) that covers the third gate field plate (107).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the semiconductor component of Nobuo with the third gate field plate as taught by Yoshitomo in order to improve the distortion characteristics of the high-frequency switch circuit without causing an increase in device area or an increase in manufacturing cost based thereon (see Yoshitomo).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub # 2016/0322351 to Moens et al. JP Pub # 2010109322 to Fuji Electric system Co LTD.
Moens discloses (fig. 3, par. 31-43) which discloses a semiconductor component, comprising: a substrate (fig. 3, ref. 200, par. 31); a channel layer and a barrier layer, sequentially stacked on the substrate (fig. 3, ref. 244, 246, par. 32); a source and a drain, disposed on the barrier layer (fig. 3, ref. 272, 274, par. 38); a first gate (fig. 3, ref. 276, par. 38) and a second gate (fig. 3, ref. 277, par. 38), disposed on the barrier layer and located between the source and the drain, wherein the second gate is disposed between the first gate and the drain (fig. 3, ref. 277); a first gate field plate, at least partially disposed on a side that is of the first gate and that is close to the drain (fig. 3, ref. 276, noting par. 39 "each of gate electrodes 276 and 277 has a stepped structure where the portion closest to the channel film 244 is the gate for the transistor, and portions at higher elevations and extending laterally provide shielding help to reduce gate capacitance"); and a first source field plate, wherein the first source field plate covers the first gate field plate, and the first source field plate overlaps the first gate and does not cover the first gate (fig. 3, where reference is made only to field plate portion in the lowest wiring level ref. 2821, par. 42, "The shielding structure 282, including the portions 2821 and 2822, is electrically connected to the drain/source electrode 272". Note also that portion ref. 2822 is located at a different wiring level and thus regarded as an additional field plate), or the first source field plate does not overlap the first gate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHSEN AHMADI whose telephone number is (571)272-5062. The examiner can normally be reached M-F: 9:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHSEN AHMADI/ Primary Examiner, Art Unit 2896
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