DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 29, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7 and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ramamurthy et al. US2022/0086577 (called Ramamurthy hereinafter).
Regarding independent claim 1, Ramamurthy teaches a fault detection circuit (Fig. 1; fault detection circuit 122), comprising:
a plurality of inputs (Fig. 1; para [0021]; inputs 144 and 146) each adapted for coupling to a resistance network (Fig. 1; para [0021]; each resistive path 124 has a resistor); and
a current source circuit (Fig. 1; para [0021]; power supply input 180 with PVDD and input 182 to ground) selectively coupled to each of the plurality of inputs to detect a fault condition (para [0019]).
Regarding independent claim 7, Ramamurthy teaches a semiconductor device (Fig. 1; para [0058]), comprising:
a semiconductor die (Fig. 1; para [0058]) including a plurality of input terminals (Fig. 1; para [0021]; inputs 144 and 146) each adapted for coupling to a resistance network (Fig. 1; para [0021]; each resistive path 124 has a resistor); and
a fault detection circuit (Fig. 1; fault detection circuit 122) formed on the semiconductor die, wherein the fault detection circuit includes a current source circuit (Fig. 1; para [0021]; power supply input 180 with PVDD and input 182 to ground) selectively coupled to each of the plurality of input terminals to detect a fault condition (para [0019]).
Regarding independent claim 14, Ramamurthy teaches a method of making a semiconductor device (Fig. 1; para [0058]), comprising:
providing a semiconductor die (Fig. 1; para [0058]) including a plurality of input terminals (Fig. 1; para [0021]; inputs 144 and 146) each adapted for coupling to a resistance network (Fig. 1; para [0021]; each resistive path 124 has a resistor); and
forming a fault detection circuit (Fig. 1; fault detection circuit 122) on the semiconductor die, wherein forming the fault detection circuit includes forming a current source circuit (Fig. 1; para [0021]; power supply input 180 with PVDD and input 182 to ground) selectively coupled to each of the plurality of input terminals to detect a fault condition (para [0019]).
Allowable Subject Matter
Claims 2-6, 8-13 and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the prior arts of record taken alone or in combination fail to teach or suggest:
“wherein the current source circuit includes: a first current source; a first switching circuit coupled between the first current source and a first node; a first resistor coupled between the first node and a first input of the plurality of inputs; a second switching circuit coupled between the first input and a power supply conductor; and a third switching circuit coupled between the first node and a second node.”
Claims 3 and 4 are indicated as allowable subject matter for depending on claim 2.
Regarding claim 5, the prior arts of record taken alone or in combination fail to teach or suggest:
“wherein the current source circuit includes: a current source; a first switching circuit coupled between the current source and a first node; a first resistor coupled to a first input of the plurality of inputs; a second switching circuit coupled between the first input and a power supply conductor; and a third switching circuit coupled between the first resistor and the first node.”
Claim 6 is indicated as allowable subject matter for depending on claim 5.
Regarding claim 8, the prior arts of record taken alone or in combination fail to teach or suggest:
“wherein the current source circuit includes: a first current source; a first switching circuit coupled between the first current source and a first node; a first resistor coupled between the first node and a first input terminal of the plurality of input terminals; a second switching circuit coupled between the first input and a power supply conductor; and a third switching circuit coupled between the first node and a second node.”
Claims 9-11 and 13 are indicated as allowable subject matter for depending on claim 8.
Regarding claim 12, the prior arts of record taken alone or in combination fail to teach or suggest:
“wherein the current source circuit includes: a current source; a first switching circuit coupled between the current source and a first node; a first resistor coupled to a first input of the plurality of inputs; a second switching circuit coupled between the first input and a power supply conductor; and a third switching circuit coupled between the first resistor and the first node.”
Regarding claim 15, the prior arts of record taken alone or in combination fail to teach or suggest:
“wherein forming the current source circuit includes: providing a first current source; providing a first switching circuit coupled between the first current source and a first node; providing a first resistor coupled between the first node and a first input terminal of the plurality of input terminals; providing a second switching circuit coupled between the first input and a power supply conductor; and providing a third switching circuit coupled between the first node and a second node.”
Claims 16-18 are indicated as allowable subject matter for depending on claim 15.
Regarding claim 19, the prior arts of record taken alone or in combination fail to teach or suggest:
“wherein forming the current source circuit includes: providing a current source; providing a first switching circuit coupled between the current source and a first node; providing a first resistor coupled to a first input of the plurality of inputs; providing a second switching circuit coupled between the first input and a power supply conductor; and providing a third switching circuit coupled between the first resistor and the first node.”
Claim 20 is indicated as allowable subject matter for depending on claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dewan et al. discloses “Implementation to detect failure or fault on an analog input path for single analog input functional safety applications” (see US2022/0276323)
Kiuchi discloses “Semiconductor device, battery state monitoring module, and vehicle system” (see US2013/0325303)
Westbrook et al. discloses “Testing systems and methods” (see US2016/0084902)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID B FREDERIKSEN whose telephone number is (571)272-8152. The examiner can normally be reached M-F 8am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at (571)272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID B FREDERIKSEN/Examiner, Art Unit 2858
/HUY Q PHAN/Supervisory Patent Examiner, Art Unit 2858
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