DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement(s)
The Information Disclosure Statement(s) filed on May 29, 2024 and October 21, 2024 were considered by the Examiner.
Election/Restrictions
Applicant's election of Group I and Species A, Sub-species a1 in the reply filed on June 26, 2026 is acknowledged.
Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement with regard to the restriction between Groups I and II, or with regard to the restriction between Species A and B, the election of Group I and Species A has been treated as an election without traverse (MPEP § 818.01(a)). As the election of Group I and Species A was made without traverse, the requirement is deemed proper and is therefore made FINAL.
With regard to the restriction between Sub-species a1 and a2, Applicant’s arguments are persuasive. Accordingly, the restriction between Sub-species a1 and a2 is withdrawn. Accordingly, all claims 1-18 of Group I were examined for patentability.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 includes “an active passive interposer die” and it is unclear how an interposer die can be active and passive at the same time. For the purposes of examination, this will be interpreted to mean “an active or passive interposer die.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5 and 8-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20240105545A1 (“Lu”) in view of US20150371938A1 (“Katkar”).
RE: Claim 1, Lu discloses An integrated circuit (IC) chip complex (100 in FIG. 9), comprising:
an interposer (160, [0035]), the interposer includes an interconnect (164, [0036]) formed in a back end of the line (BEOL) region (165, [0036], [0023]);
at least a first (IC) die (left 122, [0038]) of a first common tier (120, [0020]) hybrid bonded to a first side of the interposer (top side of 160; Lu teaches an intermediate interposer 160 to which the multiple chiplets are hybrid bonded to, [0035]; 122 are chiplets, [0038]; Accordingly, Lu teaches chiplets 122 are hybrid bonded to the interposer 160; FIG. 9 shows chiplets 122 are hybrid bonded to top side of interposer 160); and
at least two or more second (IC) dies (102, [0024]) of a second common tier (110, [0021]) hybrid bonded to a second side of the interposer (bottom side of 160; Lu teaches an intermediate interposer 160 to which the multiple chiplets are hybrid bonded to, [0035]; 102 are chiplets, [0024]; Accordingly, Lu teaches chiplets 102 are hybrid bonded to the interposer 160; FIG. 9 shows chiplets 102 are hybrid bonded to bottom side of interposer 160).
Lu does not explicitly disclose:
the interposer is a passive interposer.
In the same field of endeavor, Katkar discloses:
An interposer may be an IC, and an interposer may be a passive or an active IC, where the latter includes one or more active devices, such as transistors for example, and the former does not include any active device, [0002].
Accordingly, before the effective filing date of the claimed invention there was a need to determine if the interposer 160 would be active or passive.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the interposer 160 be a passive interposer as this would have been obvious to try since a passive interposer is one solution for an interposer identified by Katkar, and this would have had a reasonable expectation of success, see MPEP 2143.
RE: Claim 2, Lu in view of Katkar discloses The IC chip complex of claim 1, wherein the passive interposer covers an entirety of the first IC die (Lu FIG. 9 shows the interposer 160 would cover an entirety of the first left IC die 122 when viewed in an upward direction from 110).
RE: Claim 3, Lu in view of Katkar discloses The IC chip complex of claim 2, wherein the passive interposer covers an entirety of a second IC die present in the first common tier (Lu FIG. 9 shows the interposer 160 would cover an entirety of a second righthand IC die 122 present in the first common tier 120, when viewed in an upward direction from 110).
RE: Claim 4, Lu in view of Katkar discloses The IC chip complex of claim 2, wherein the passive interposer covers an entirety of a first one of the at least two or more second IC dies present in the second common tier (Lu FIG. 9 shows the interposer 160 would cover an entirety of left 102 present in the second common tier 110 when viewed in a downward direction from 120).
RE: Claim 5, Lu in view of Katkar discloses The IC chip complex of claim 4, wherein the passive interposer covers an entirety of a second one of at least two or more second IC dies present in the second common tier (Lu FIG. 9 shows the interposer 160 would cover an entirety of a second righthand one of at least two or more second IC dies 102 present in the second common tier 110, when viewed in a downward direction from 120).
RE: Claim 8, Lu in view of Katkar discloses The IC chip complex of claim 1, wherein the BEOL region defines the first and second sides of the passive interposer (Katkar discloses in FIG. 8: BEOL stack 315, namely a stack without a substrate, may be provided with a configuration to provide an interposer-like functionality for a stacked die assembly, such as a 3D stacked IC device 300, [0053];
a BEOL stack 315 may be formed independently from a large integrated circuit die to reduce the number of BEOL operations used in forming such a large integrated circuit die. This may improve yield of such large integrated circuit die by avoiding many BEOL operations, which operations may effectively be transferred to formation of a BEOL stack 315. Such BEOL stack 315 may be substantially less expensive to manufacture than a large integrated circuit die, and accordingly such BEOL stack 315 may be tested prior to interconnection to any integrated circuit die, [0065];
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the interposer 160 to include only the BEOL structure 165, and be without the substrate 161 as taught by Katkar in order to reduce manufacturing costs as further taught by Katkar while still allowing 160 to function as an interposer; As a result, the BEOL region 165 of 160 would define the top and bottom sides of the passive interposer 160).
RE: Claim 9, Lu in view of Katkar discloses The IC chip complex of claim 1 further comprising:
a silicon block (From Lu: 150; 150 is formed from a silicon substrate, [0026]) disposed over the first IC die.
RE: Claim 10, Lu in view of Katkar discloses The IC chip complex of claim 1, wherein the first IC die is a memory die (From Lu: 122 is a cache die, [0021]).
RE: Claim 11, Lu in view of Katkar discloses The IC chip complex of claim 1, wherein the first IC die is a logic die (From Lu: 122 is a graphics processing unit, central processing unit, or machine learning logic die, [0021]).
Claims 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Katkar as applied to claim 1, further in view of US20220399294A1 (“Dogiamis”).
RE: Claim 6, Lu in view of Katkar discloses The IC chip complex of claim 1, wherein the passive interposer comprises:
a substrate (From Lu: 161, [0036]); and
vias (From Lu: 168, [0036]) formed through the substrate, the vias coupled to the interconnect (Lu FIG. 9 shows the vias 168 are coupled to 164).
Lu in view of Katkar does not explicitly disclose the substrate is a thinned substrate.
However in the same field of endeavor, Dogiamis discloses in FIG. 1A:
an interposer (104, [0022]) including a thinned substrate (101, [0022]; wafer thinning is performed on standoff layer 101, [0054]).
Dogiamis discloses additional processing operations may be performed on the first standoff layer 101-1, for example, wafer thinning, top surface TSV 113 reveal, TSV pad creation, and forming HB interfaces 180-5A, 180-1B, [0047].
Dogiamis identifies HB as hybrid bonding, [0021].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to thin the substrate 161 as taught by Dogiamis in order to reveal the vias 168 and/or form hybrid bond interfaces as further taught by Dogiamis.
RE: Claim 7, Lu in view of Katkar, Dogiamis discloses The IC chip complex of claim 6, wherein the passive interposer includes passive routing without a presence of transistors (Lu teaches 160 is an intermediate interposer 160, [0035]. The intermediate interposer may provide additional routing, [0035]; As modified, the interposer 160 is a passive interposer; Accordingly, the routing in 160 would be passive routing; Further, Katkar teaches An interposer may be an IC, and an interposer may be a passive or an active IC, where the latter includes one or more active devices, such as transistors for example, and the former does not include any active device, [0002]; Accordingly, as modified, as the interposer 160 is passive, 160 would not include any transistors).
Claim 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Katkar as applied to claim 1, further in view of US20100044095A1 (“Kuczynski”).
RE: Claim 12, Lu in view of Katkar does not explicitly disclose: The IC chip complex of claim 1 further comprising:
an active or passive interposer die stacked with the passive interposer.
However, in the same field of endeavor, Kuczynski discloses that an interposer and a module substrate are examples of an interconnect substrate, [0039].
Lu teaches 220 in FIG. 11 is a module substrate, [0039].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the module substrate 220 in FIG. 11 of Lu with an interposer as this would have been simple substitution as both function as interconnect substrates as taught by Kuczynski and the results would have been predictable, see MPEP 2143.
Further Katkar discloses:
An interposer may be an IC, and an interposer may be a passive or an active IC, where the latter includes one or more active devices, such as transistors for example, and the former does not include any active device, [0002].
Accordingly, before the effective filing date of the claimed invention there was a need to determine if the interposer 220 would be active or passive.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the interposer 220 be an active interposer as this would have been obvious to try since an active interposer is one solution for an interposer identified by Katkar, and this would have had a reasonable expectation of success, see MPEP 2143. As a result, the active interposer 220 would be stacked with the passive interposer 160.
Claim(s) 13-14 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Katkar.
RE: Claim 13, Lu discloses An integrated circuit (IC) chip package (200 in FIG. 11), comprising:
a substrate (220); and
a chip complex (100 as shown in FIG. 9) mounted to the substrate, the chip complex comprising:
a interposer (160, [0035]);
at least a first (IC) die (left 122, [0038]) of a first common tier (120, [0020]) hybrid bonded to a first side of the interposer (top side of 160; Lu teaches an intermediate interposer 160 to which the multiple chiplets are hybrid bonded to, [0035]; 122 are chiplets, [0038]; Accordingly, Lu teaches chiplets 122 are hybrid bonded to the interposer 160; FIG. 9 shows chiplets 122 are hybrid bonded to top side of interposer 160); and
at least two or more second (IC) dies (102, [0024]) of a second common tier (110, [0021]) hybrid bonded to a second side of the interposer (bottom side of 160; Lu teaches an intermediate interposer 160 to which the multiple chiplets are hybrid bonded to, [0035]; 102 are chiplets, [0024]; Accordingly, Lu teaches chiplets 102 are hybrid bonded to the interposer 160; FIG. 9 shows chiplets 102 are hybrid bonded to bottom side of interposer 160).
Lu does not explicitly disclose:
the interposer is a passive interposer.
In the same field of endeavor, Katkar discloses:
An interposer may be an IC, and an interposer may be a passive or an active IC, where the latter includes one or more active devices, such as transistors for example, and the former does not include any active device, [0002].
Accordingly, before the effective filing date of the claimed invention there was a need to determine if the interposer 160 would be active or passive.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the interposer 160 be a passive interposer as this would have been obvious to try since a passive interposer is one solution for an interposer identified by Katkar, and this would have had a reasonable expectation of success, see MPEP 2143.
RE: Claim 14, Lu in view of Katkar discloses The chip package of claim 13, wherein the passive interposer covers an entirety of the first IC die present in the first common tier and all the second IC dies present in the second common tier (Lu FIG. 9 shows interposer 160 covers an entirety of the first left IC die 122 present in the first common tier 120 when viewed in an upward direction from 110, and covers all the second IC dies 102 present in the second common tier 110 when viewed in a downward direction from 120).
RE: Claim 18, Lu in view of Katkar discloses The chip package of claim 13, wherein the first IC die is a memory die or a logic die (From Lu: 122 is a cache die, a graphics processing unit, central processing unit, or machine learning logic die, [0021]).
Claims 15, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Katkar as applied to claim 14, further in view of Kuczynski.
RE: Claim 15, Lu in view of Katkar does not explicitly disclose The chip package of claim 14, wherein the substrate (From Lu: 220 in FIG. 11) includes passive routing without a presence of transistors.
However, in the same field of endeavor, Kuczynski discloses that an interposer and a module substrate are examples of an interconnect substrate, [0039].
Lu teaches 220 in FIG. 11 is a module substrate, [0039].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the module substrate 220 in FIG. 11 of Lu with an interposer as this would have been simple substitution as both function as interconnect substrates as taught by Kuczynski and the results would have been predictable, see MPEP 2143.
Further Katkar discloses:
An interposer may be an IC, and an interposer may be a passive or an active IC, where the latter includes one or more active devices, such as transistors for example, and the former does not include any active device, [0002].
Katkar further teaches an interposer includes at least one through-substrate-via, [0002].
Accordingly, before the effective filing date of the claimed invention there was a need to determine if the interposer 220 would be active or passive.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the interposer 220 be a passive interposer with a through-substrate via as this would have been obvious to try since a passive interposer is one solution for an interposer identified by Katkar, and this would have had a reasonable expectation of success, see MPEP 2143. Accordingly, as the interposer/substrate 220 is passive, the through-substrate via would correspond to the claimed passive routing, and further 220 would not include any transistors.
RE: Claim 17, Lu in view of Katkar, Kuczynski discloses The chip package of claim 15, wherein the passive interposer (From Lu: 160) comprises:
an interconnect (From Lu: 164, [0036]) disposed in a BEOL region (165, [0036], [0023]), the BEOL region comprising the first and second sides of the passive interposer (Katkar discloses in FIG. 8: BEOL stack 315, namely a stack without a substrate, may be provided with a configuration to provide an interposer-like functionality for a stacked die assembly, such as a 3D stacked IC device 300, [0053];
a BEOL stack 315 may be formed independently from a large integrated circuit die to reduce the number of BEOL operations used in forming such a large integrated circuit die. This may improve yield of such large integrated circuit die by avoiding many BEOL operations, which operations may effectively be transferred to formation of a BEOL stack 315. Such BEOL stack 315 may be substantially less expensive to manufacture than a large integrated circuit die, and accordingly such BEOL stack 315 may be tested prior to interconnection to any integrated circuit die, [0065];
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the interposer 160 to include only the BEOL structure 165, and be without the substrate 161 as taught by Katkar in order to reduce manufacturing costs as further taught by Katkar while still allowing 160 to function as an interposer; As a result, the BEOL region 165 of 160 in Lu would comprise the top and bottom sides of the passive interposer 160).
Claims 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Katkar, Kuczynski as applied to claim 15, further in view of Dogiamis.
RE: Claim 16, Lu in view of Katkar, Kuczynski discloses The chip package of claim 15, wherein the passive interposer comprises:
an interconnect (From Lu: 164, [0036]) disposed in a BEOL region (165, [0036], [0023]) of a substrate (161, 163); and
vias (From Lu: 168, [0036]) formed through the substrate, the vias coupled to the interconnect (Lu FIG. 9 shows the vias 168 are coupled to 164).
Lu in view of Katkar, Kuczynski does not explicitly disclose the substrate is a thinned substrate.
However in the same field of endeavor, Dogiamis discloses in FIG. 1A:
an interposer (104, [0022]) including a thinned substrate (101, [0022]; wafer thinning is performed on standoff layer 101, [0054]).
Dogiamis discloses additional processing operations may be performed on the first standoff layer 101-1, for example, wafer thinning, top surface TSV 113 reveal, TSV pad creation, and forming HB interfaces 180-5A, 180-1B, [0047].
Dogiamis identifies HB as hybrid bonding, [0021].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to thin the portion 161 of the substrate 161, 163 as taught by Dogiamis in order to reveal the vias 168 and/or form hybrid bond interfaces as further taught by Dogiamis.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights