CTNF 18/676,726 CTNF 83454 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-26 AIA Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. Information Disclosure Statement The information disclosure statement(s) (IDS) submitted on 05/29/24 was/were received by the Examiner before the issuance/mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) has/have been considered (except for anything in foreign language non-accompanied by an English translation) by the Examiner. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-3 and 5 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lee (US 11,335,687; cited on IDS) . a. Re claim 1, Lee discloses a memory device comprising: a substrate LS (see figs. 2A-5 and related text; see remaining of disclosure for more details); a unit cell selection transistor Tr on (i.e. mechanically connected to, directly or indirectly) the substrate (Tr is on the substrate LS by being connected to it via BL); and a capacitor structure CAP&PL on (i.e. mechanically connected to, directly or indirectly) the unit cell selection transistor, the capacitor structure comprising a common electrode PL connected (via PN, DE, SN; see fig. 2C) to the unit cell selection transistor, a plurality of plate electrodes (horizontal portions of SN) facing the common electrode (see fig. 2C&5), and a capacitor dielectric layer DE arranged between the common electrode and the plurality of plate electrodes, wherein the common electrode comprises a vertical extension portion (explicit on fig. 2C) in contact (via PN, DE, SN) with the unit cell selection transistor and extending in a vertical direction, and a plurality of horizontal extension portions PN (labeled and unlabeled; three are shown on fig. 2C) extending in a first horizontal direction D2 (see figs. 2B-2C) from a side wall of the vertical extension portion and apart from each other in the vertical direction, and wherein each of the plurality of plate electrodes extends in a second horizontal direction D3 between the plurality of horizontal extension portions (explicit in view of figs. 2A-C&5), the second horizontal direction being perpendicular to the first horizontal direction. b. Re claim 2, the plurality of horizontal extension portions comprises: a first (top) horizontal extension portion facing an upper surface of a plate electrode (top one) from among the plurality of plate electrodes with the capacitor dielectric layer therebetween (explicit on figs. 2A-C&5); and a second (middle) horizontal extension portion spaced apart from the first horizontal extension portion, in the vertical direction, with the plate electrode therebetween, the second horizontal extension portion facing a lower surface of the plate electrode with the capacitor dielectric layer therebetween (explicit on figs. 2A-C&5). c. Re claim 3, a side wall of each of the plurality of plate electrodes in the first horizontal direction faces the side wall of the vertical extension portion, with the capacitor dielectric layer therebetween (explicit on figs. 2A-C&5). d. Re claim 5, the plurality of horizontal extension portions and the plurality of plate electrodes are arranged at different vertical levels from each other (explicit on fig. 2C) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 4 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 11,335,687; cited on IDS) . a. Re claim 4, Lee discloses all the limitations of claim 1 as stated above except explicitly for the memory device of claim 1, further comprising an insulating structure surrounding the capacitor structure, wherein both side walls of each of the plurality of horizontal extension portions in the second horizontal direction are in contact with the insulating structure. However, it is conventionally known in the art to form interlayer dielectric layers between over and between structural parts of a memory device structure in order to protect, seal and electrically isolate said structural parts. As such, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided the memory device of claim 1, further comprising an insulating structure (in for of interlayer dielectric layers) surrounding the capacitor structure, wherein both side walls of each of the plurality of horizontal extension portions in the second horizontal direction are in contact with the insulating structure, and this in order to protect, seal and electrically isolate the memory structure on fig. 2A. b. Re claim 6, Lee discloses all the limitations of claim 1 as stated above except explicitly for the capacitor dielectric layer comprising ferroelectrics. However, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided the capacitor dielectric layer comprising ferroelectrics for an application requiring the capacitor dielectric to comprise ferroelectrics . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 11-20 are allowed. 12-151-08 AIA 07-43 12-51-08 Claim s 7-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Im et a. (US 2022/0130430) and Lee (US 2021/0242210) disclose structures similar to the claimed invention . Any inquiry concerning this communication or earlier communications from the examiner should be directed to PENIEL M GUMEDZOE whose telephone number is (571)270-3041. The examiner can normally be reached M-F: 9:00AM - 5:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PENIEL M GUMEDZOE/Primary Examiner, Art Unit 2899 Application/Control Number: 18/676,726 Page 2 Art Unit: 2899 Application/Control Number: 18/676,726 Page 3 Art Unit: 2899 Application/Control Number: 18/676,726 Page 4 Art Unit: 2899 Application/Control Number: 18/676,726 Page 5 Art Unit: 2899 Application/Control Number: 18/676,726 Page 6 Art Unit: 2899
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