DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Request for Continued Examination
1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 1/14/2026 has been entered.
Claim Rejections - 35 USC § 112
2. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
3. Claims 14-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claims 14-15, “the control circuit” has not been previously defined, therefore this term is indefinite.
Examiner Notes
4. Examiner cites particular paragraphs, columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sestok et al. (US. Pub. 20180180652; hereinafter “Sestok”).
Regarding claim 1, Sestok discloses a circuit (an impedance analyzer 201 in Fig. 2) comprising:
a driver circuit (such as a clock synthesizer 12 ) having a first frequency control input (the clock synthesizer12 receives a first frequency input signal at its input from GPIO 10 of a microcontroller unit MCU 6) and a driver output (an output port of the synthesizer 12 that outputs a modified frequency signal to a DUT 4), the driver circuit
configurable to provide a signal having a first frequency and update set an attribute of the signal at a second frequency responsive to states of the first frequency control inputs (the clock synthesizer 12 configured to can change the input clock frequency provided by GPIO 10 by multiplying the input frequency by an integer and then dividing by another integer to get an output clock frequency, see Fig. 2 and [0067]);
a processing circuit (such as MCU 12) having a sense input (an input terminal 42 received a measurement signal from the DUT4), a second frequency control input (such as a frequency input fS in Fig. 2), and a parameter output (a parameter output from an ADC 34).
Regarding claim 14, Sestok discloses the circuit of claim 1, wherein the driver circuit, the processing circuit, and the control circuit are part of an integrated circuit (see Fig. 2 and [0004]).
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Sestok in view of Laletin et al. (US. Pub. 20030206021; hereinafter “Laletin”).
Regarding claim 15, Sestok discloses the circuit of claim 1, except for explicitly specifying that wherein the driver circuit, the processing circuit, and the control circuit are part of a battery management system. Laletin discloses, in fig. 1b, a battery management system for measuring an impedance of a battery under tested, comprising a driver circuit (22, 48), a processing circuit (30), and the control circuit (40) It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the impedance analyzer of Sestok for testing the battery as taught by Laletin, for the purpose of providing the process having accurate time-domain measurement and analysis to allow characterization of the system.
9. Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Sestok in view of Hill et al. (US. Pub. 20230031969; hereinafter “Hill”).
Regarding claim 21, Sestok discloses the circuit of claim 1, except for explicitly specifying wherein the processing circuit is configurable to provide parameters of a battery.
Hill discloses a test apparatus (Fig. 3A) configured to test a battery (5) and obtain impedance parameters of the battery (see paragraphs [0076-77]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the impedance analyzer of Sestok having the processing circuit is configurable to provide parameters of a battery as taught by Hill, for the purpose of providing the impedance measurement that reduces or eliminates the rogue wave artifact with excitation time records which excite a test device using an excitation signal including a root mean squared current or a root mean squared voltage in a sequence of one or more frequency group.
Regarding claim 22, Sestok and Hill disclose the circuit of claim 21, Hill further teaches wherein the parameters include impedance spectroscopy parameters (see at least in [0069-70]).
Allowable Subject Matter
10. Claims 2-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
11. Claims 16-20 and 23 are allowed over the prior arts of record.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 16, the cited reference arts of record, alone or in combination, do not disclose nor fairly suggest:
“…providing a second signal based on the first signal, and updating the second signal at a second frequency, to a device under test (DUT); obtaining sense signal samples from the DUT at a third frequency, in which a fourth frequency of the clock signal is a multiple of the first, second, and third frequencies; processing the sense signal samples; determining a parameter of the DUT based on a result of processing the sense signal samples; and performing one or more operations based on the parameter.” in combination with all other elements as claimed in claim 16.
As to claim(s) 17-20 and 23, the claims are allowed as they further limit allowed claim 16.
Conclusion
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANG LE whose telephone number is (571)272-9349. The examiner can normally be reached on Monday thru Friday 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached on (571) 272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THANG X LE/Primary Examiner, Art Unit 2858
2/10/2026