DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 05/29/2024 have been accepted by the examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 05/29/2024 & 10/23/2025. The information disclosed therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-8, 11-16 & 19-20 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Hong et al (US20200075089).
Regarding claim 1, Hong discloses a memory device(FIG 1, 100) comprising: a memory cell array including a first memory cell coupled to a first word line and a second memory cell coupled to a second word line(100 comprising 104 driving word lines connected to the memory cells in 110); and a word line driver coupled to the memory cell array and configured to drive the first and second word lines with a word line signal having a pulse(FIG 3 & 5; 104 driving having WL<m-1> and WL<0> having a pulse) wherein a leading edge of the word line signal pulse is delayed for the word line signal applied to the first word line relative to the word line signal applied to the second word line ( FIG 5; a leading edge of signal WL<m-1> is delayed relative to WL<0>).
Regarding claim 2, Hong discloses wherein the word line signal pulse has a width (FIG 5; WL<m-1> and WL<0> having pulser width), and the word line signal pulse width is shorter for the word line signal applied to the first word line relative to the word line signal applied to the second word line (WL<m-1> shorter pulse width than WL<0>).
Regarding claim 5, Hong discloses further comprising a clock generator configured to generate an internal clock signal with a varying pulse width, the internal clock signal pulse width being varied by varying timing of a leading edge of the internal clock signal based on a row address (FIG 5; CKP_WL internal clocks having varied by varying timing of a leading edge e.g., CKP_WL fast and CKP_WL slow).
Regarding claim 6, Hong discloses wherein the word line signal pulse for the word line signal applied to the first word line is shorter than the word line signal pulse for the word line signal applied to the second word line (FIG 5; WL<m-1> pulse shorter than WL<0> pulse).
Regarding claim 7, Hong discloses wherein a first read margin of the first memory cell is substantially the same as a second read margin of the second memory cell (FIG 5; reading margin e.g., T1 for WL<m-1> connected to memory cell substantially same as WL<0> connected to second memory cell).
Regarding claim 8, Hong discloses a memory device comprising a first memory cell and configured to perform a read operation of the first memory cell in which a pulse of a word line signal used to read the first memory cell has a leading edge the timing of which is based on a row address of the first memory cell (FIG 1, 3 & 5; 100 comprising 104 driving word lines connected to the memory cells in 110, wherein 104 driving having WL<m-1> having a pulse and a leading edge of signal WL<m-1> is delayed relative to e.g., WL<0>).
Regarding claim 11, Hong discloses further comprising a clock generator configured to generate an internal clock signal, the clock generator being configured to receive address signals representing row addresses of the first and second memory cells, and to generate the internal clock signal with a pulse having a leading edge that is delayed for a row address corresponding to the first memory cell relative to a row address corresponding to the second memory cell (FIG 5; CKP_WL internal clocks having varied by varying timing of a leading edge e.g., CKP_WL fast 332 and CKP_WL slow 334 336).
Regarding claim 12, Hong discloses wherein: the clock generator receives an external clock signal having a pulse, and the leading edge of the internal clock signal pulse is delayed, relative to a leading edge of the external clock signal pulse, for the row address corresponding to the first memory cell relative to the row address corresponding to the second memory cell (FIG 5; CKP having pulse, 338 is delayed relative to CKP pulse, and 338 is delayed than 332).
Regarding claim 13, Hong discloses further comprising: a memory cell array including the first memory cell and a second memory cell(FIG 1 & 3; 100 comprising 110 and memory cell on WL<m-1> and WL<0> ), and a word line driver coupled to the memory cell array(104 coupled to 110), wherein: the first memory cell is coupled to a first word line (WL<m-1>), the second memory cell is coupled to a second word line(WL<0>), the word line driver is configured to drive the first and second word lines with the word line signal(FIG 3 & 5; 104 driving having WL<m-1> and WL<0> having word line signal e.g., a pulse), and a leading edge of a word line signal pulse is delayed for the word line signal applied to the first word line relative to the word line signal applied to the second word line( FIG 5; a leading edge of signal WL<m-1> is delayed relative to WL<0>).
Regarding claim 14, Hong discloses wherein a first read margin of the first memory cell is substantially the same as a second read margin of the second memory cell (FIG 5; reading margin e.g., T1 for WL<m-1> connected to memory cell substantially same as WL<0> connected to second memory cell).
Regarding claim 15, Hong discloses a method of operating a memory, the method comprising: generating a first word line signal having a first word line signal pulse having a first word line signal pulse width, and applying the first word line signal to a first memory cell of a memory cell array; (FIG 1, 3 5; WL<m-1> having a first wordline pulse and applying memory cell on WL<m-1>) and generating a second word line signal having a second word line signal pulse having a second word line signal pulse width, and applying the second word line signal to a second memory cell of the memory cell array(FIG 1, 3 5; WL<0> having a second wordline pulse and applying memory cell on WL<0>), the generating of the first word line signal including delaying a leading edge of the first word line signal pulse relative to a leading edge of the second word line signal pulse ( FIG 5; a leading edge of signal WL<m-1> is delayed relative to WL<0>).
Regarding claim 16, Hong discloses wherein the first word line signal pulse width is generated to be shorter than the second word line signal pulse width FIG 5; WL<m-1> pulse shorter than WL<0> pulse).
Regarding claim 19, Hong discloses wherein generating the first and second word line signals includes controlling the first word line signal pulse width to be shorter than the second word line signal pulse width (FIG 5; WL<m-1> pulse shorter than WL<0> pulse).
Regarding claim 20, Hong discloses further comprising generating an internal clock signal having an internal clock signal pulse, the generating the internal clock signal including changing a timing of a leading edge of the internal clock signal pulse based on row addresses of the first and second memory cells, wherein the changing timing of the leading edge of the internal clock signal pulse includes delaying the leading edge of the internal clock signal pulse for a row address corresponding to the first memory cell relative to a row address corresponding to the second memory cell(FIG 5; CKP_WL internal clocks having varied by varying timing of a leading edge e.g., CKP_WL fast 332 and CKP_WL slow 334 336).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4, 9-10 & 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al.
Regarding claim 3, Hong discloses further comprising a sense amplifier array configured to read data from the first and second memory cells(FIG 3; sense amplifier 112 reading data of memory cells), wherein: a distance from the first word line to the sense amplifier array is a first distance(WL<m-1> distance e.g., the placement of WL<m-1> from 112 is a distance), a distance from the second word line to the sense amplifier array is a second distance(WL<0> second distance from 112).
However, Hong does not disclose and the first distance is less than the second distance, discloses the However, the first distance is less than the second distance is in regards to particular placement of the different word lines from the sense amplifier was held to be an obvious matter of design choice. Therefore, the WL<m-1> and WL<0> can be placed so the first distance is less than the second distance. Please see MPEP 2144.04.
Regarding claim 4, Hong discloses further comprising: a first sense amplifier and a first bit line that couples the first sense amplifier to the first memory cell(FIG 3; 112 coupled to BL<0> connected to first memory cell e.g., cell on WL<m-1>); and a second sense amplifier and a second bit line that couples the second sense amplifier to the second memory cell(FIG 3; 112 coupled to BLB<0> connected to second memory cell e.g., cell on WL<0>); wherein: a length of the first bit line from the first sense amplifier to the first memory cell is a first distance(cell on WL<m-1> connected to BL<0> coupled to 112 is a first distance), a length of the second bit line from the second sense amplifier to the second memory cell is a second distance cell on WL<0> connected to BLB<0> coupled to 112 is a second distance), and the first distance is less than the second distance ( FIG 3; BL<0> first distance on first cell is greater than the second distance BLB<0> on second cell). However, BL<0> on cell first cell, and BLB<0> on second cell, the distance can be placed so the first distance is less than the second distance. Please see MPEP 2144.04.
Regarding claim 9, Hong discloses further comprising: a second memory cell; and a sense amplifier array configured to read data from the first and second memory cells(FIG 3; 112), wherein: the first memory cell is coupled to a first word line(first memory cell coupled to WL<m-1>), the second memory cell is coupled to a second word line(second memory coupled to WL<0>), a distance from the first word line to the sense amplifier array is a first distance(WL<m-1> distance e.g., the placement of WL<m-1> from 112 is a distance), a distance from the second word line to the sense amplifier array is a second distance that is greater than the first distance(WL<0> second distance from 112), the pulse of the word line signal has a width(FIG 5; WL<m-1> and WL<0> having pulse width), and the width is greater for the word line signal applied to the second word line relative to the word line signal applied to the first word line(WL<0> less width than WL<m-1>). Note, a distance from the second word line to the sense amplifier array is a second distance that is greater than the first distance in regards to particular placement of the different word lines from the sense amplifier was held to be an obvious matter of design choice. Therefore, the WL<m-1> and WL<0> can be placed so the first distance is less than the second distance. Please see MPEP 2144.04.
Regarding claim 10, Hong discloses wherein the leading edge of the pulse of the word line signal is not delayed for the word line signal applied to the second word line (FIG 3 & 5; the leading edge of the pulse of WL<0> is not delayed in relative to WL<m-1>).
Regarding claim 17, Hong discloses further comprising reading data from the first and second memory cells using a sense amplifier array,(FIG 3; 112) wherein: a distance from the first word line to the sense amplifier array is a first distance), a distance from the second word line to the sense amplifier array is a second distance(WL<m-1> distance from 112 and WL<0> distance from 112), and the first distance is less than the second distance(WL<m-1> distance from 112 is greater WL<0> distance from 112), the reading the data from the first and second memory cells including ending a read operation of the first memory cell after a first elapsed time and ending a read operation of the second memory cell after a second elapsed time, the first elapsed time being shorter than the second elapsed time (FIG 5; WL<m-1> reading timing from shorter than the second time elapsed on WL<0> e.g., due to the delay on WL<m-1). Note the first distance is less than the second distance is in regards to particular placement of the different word lines from the sense amplifier was held to be an obvious matter of design choice. Therefore, the WL<m-1> and WL<0> can be placed so the first distance is less than the second distance. Please see MPEP 2144.04.
Regarding claim 18, Hong discloses further comprising: driving the sense amplifier array with a first sense amplifier enable signal having a first sense amplifier enable signal pulse to read the first memory cell(FIG 3; sensing enable from 120 to 112 to read the first cell e.g., on WL<m-1>). ; and driving the sense amplifier array with a second sense amplifier enable signal having a second sense amplifier enable signal pulse to read the second memory cell FIG 3; sensing enable from 120 to 112 to read the first cell e.g., on WL<0>), wherein: the first elapsed time is a time from the leading edge of the first word line signal pulse to a leading edge of the first sense amplifier enable signal pulse(FIG 5; 338), and the second elapsed time is a time from the leading edge of the second word line signal pulse to a leading edge of the second sense amplifier enable signal pulse(FIG 5; 330).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Hong et al (US20180308533 FIG 1-2A discloses 110 comprising WL1 connected to MC11, and WL4 connected to MC14 having different pulse widths).
Takahashi et al (US20040076054 FIG 3-4B; discloses WL1 and WL2, wherein a leading edge of WL1 is delayed, and sense amplifier 12 connected to MC1 and MC2, wherein WL2 is less in distance from 12 relative to WL1).
Yamamoto et al (US5909407 FIG 8; WL2 having a leading edge delayed than WL1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
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/MUNA A TECHANE/Primary Examiner, Art Unit 2827
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