DETAILED ACTION
This action is responsive to the following communications: the Application filed on March 3, 2026.
Claims 1, 3-8, 12-17 and 21 are pending. Claims 2, 9-11 and 18-20 are canceled. Claims 1, 6-7, 12 and 15 are amended. Claim 21 is newly added. Claims 1, 12 and 21 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were received on March 11, 2026. These drawings are acceptable.
Claim Objections
Claims 8, 12 and 16 are objected to because of the following informalities:
In claim 8, lines 1, “where programming” should be --wherein programming--.
In claim 12, lines 6, “the third channel and the fourth channel correspond to a second select line” should be --the third plug and the fourth plug correspond to a second select line--.
In claim 16, lines 1, “where programming” should be --wherein programming--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 and 16-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claims 8 and 16, each of claim recites “where programming the selected memory cells comprises:”. However, independent claims 1 and 12 do not previously introduce “selected memory cells”. Claims 1 and 12 instead recite “simultaneously programming memory cells included in the first plug and the second plug”. It is unclear whether “the selected memory cells” refers to all memory cells being simultaneously programmed under claims 1 and 12, respectively; only memory cells coupled to the selected word line recited in claims 8 and 16; or another subset of memory cells. Thus, the metes and bounds of claims 8 and 16 cannot be determined with reasonable certainly.
With respect to claims 17, the claim recites “applying the program voltage to the first channel, the second channel, the third channel, and the fourth channel”. The phrase “the program voltage” lacks antecedent basis in claim 12, from which claim 17 directly depends. Claim 12 introduces “a program-enable voltage”, but does not introduce “the program voltage”. Claim 12 further recites “the selected memory cells”, although claim 12 does not previously introduce that term. Claim 12 recites only “memory cells included in” the four plugs. Thus, it is unclear which particular memory cells provide the condition that triggers the further step recited in claim 17.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6-8, 12, 16 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu (US 20190147959).
Regarding independent claim 1, Hsu discloses a method of operating a memory device [see Fig. 18, showing exemplary programming operations to program the 3D NAND flash memory block shown in FIG. 16], the method comprising:
precharging a first channel of a first plug corresponding to a first select line and a second channel of a second plug corresponding to a second select line [Hsu discloses in Figure 16 a block of a 3D NAND flash memory array that includes multiple groups of pages. Each page group contains multiple cell strings, each cell string has a channel, and each string includes a drain select gate and a source select gate, para. 109-113. A string in page group 1600a may be treated as the claimed first plug and a string in page group 1600b may be treated as the claimed second plug. The drain select gates in page group 1600a are connected to the control signal SG[0], the drain select gates in page group 1600b are connected to SG[1], para. 110. See Fig. 18: step 1801a, supplying VDD to all bit lines and pulsing all selects gates SG[0:n] of all the page groups to load VDD into all the channels of all the cell strings in each page group, para. 119. Thus, the channel of a first string under SG[0] and the channel of a second string under SG[1] are precharged to VDD];
applying a program-enable voltage to the first channel [see Fig. 18: step 1801c, applying PAGE 0 data to the bit lines and pulsing the first select gate SG[0] to load the data into the channels of the cell strings in the first page group 1600a. The bit lines with 0V (data 0) will discharge the channels of the associated strings to 0V. The cells on PAGE 0 with 0V channel voltage, the electric field between the cells' gate and their channel (which is 0V) will cause electrons to inject from their channel to the charge storage element of the cells and begin programming, para 122];
applying the program-enable voltage to the second channel [see Fig. 18: step 1801c, after PAGE 0 is loaded and programming has begun, the select gate SG[0] is turned off. The data for the next page (PAGE 1) is applied to the bit lines, and the next select gate (e.g., SG[1] associated with the page group 1) is pulsed to load the data to (Channel 1 [0:k]) and begin programming that page, para. 124]; and
simultaneously programming memory cells included in the first plug and the second plug [PAGE 0 in page group 1600a, PAGE 1 in page group 1600b and other pages up to PAGE N in page group 1600c can be loaded with different data and programmed simultaneously by applying 20V to the word line (e.g., WL[c]) that connects them together, para. 110. See Fig. 18: step 1801d, after the data for multiple pages are loaded and programming has begun, the voltages of the word lines will be maintained to allow all the pages (0 to N) to continue programming in parallel and the cells in the multiple selected pages complete their programming operation in parallel, para. 126].
Regarding claim 6, Hsu discloses wherein applying the program-enable voltage to the first channel comprises:
inputting data to a first page buffer [see Fig. 5, data stored in the data caches 502-503 can be transferred to the page buffer 501 page-by-page and then loaded into each selected block BLK0-BLKm, para. 63]; and
outputting, by the first page buffer, the program-enable voltage to a first bit line coupled to the first plug depending on the data [a selected bit line BL0-BLk can be applied with a 0V or VDD signal from the page buffer 606, para. 67. See Fig. 18: step 1801c, applying PAGE 0 data to the bit lines and pulsing the first select gate SG[0] to load the data into the channels of the cell strings in the first page group 1600a. The bit lines with 0V (data 0) will discharge the channels of the associated strings to 0V. The cells on PAGE 0 with 0V channel voltage, the electric field between the cells' gate and their channel (which is 0V) will cause electrons to inject from their channel to the charge storage element of the cells and begin programming, para 122].
Regarding claim 7, Hsu discloses wherein applying the program-enable voltage to the second channel comprises:
inputting data to a second page buffer [see Fig. 5, data stored in the data caches 502-503 can be transferred to the page buffer 501 page-by-page and then loaded into each selected block BLK0-BLKm, para. 63]; and
outputting, by the second page buffer, the program-enable voltage to a second bit line coupled to the second plug depending on the data [a selected bit line BL0-BLk can be applied with a 0V or VDD signal from the page buffer 606, para. 67. See Fig. 18: step 1801c, after PAGE 0 is loaded and programming has begun, the select gate SG[0] is turned off. The data for the next page (PAGE 1) is applied to the bit lines, and the next select gate (e.g., SG[1] associated with the page group 1) is pulsed to load the data to (Channel 1 [0:k]) and begin programming that page, para. 124].
Regarding claim 8, Hsu discloses where programming the selected memory cells comprises:
applying a pass voltage to unselected word lines among word lines coupled to the first plug and the second plug [see Fig. 18, all the unselected word lines (such as WL[1:c−1] through WL[c+1:m] for example) are supplied with a middle-high inhibit voltage (Vinh), such as 8V to 10V, para. 120]; and
applying a program voltage to a selected word line among the word lines [see Fig.18, the selected word line (such as WL[c] for example) is supplied with the program high voltage (Vpgm), such as 15V to 20V, para. 120].
Regarding independent claim 12, Hsu discloses a method of operating a memory device [see Fig. 18, showing exemplary programming operations to program the 3D NAND flash memory block shown in FIG. 16], the method comprising:
precharging a first channel of a first plug and a second channel of a second plug, wherein the first plug and the second plug correspond to a first select line [Hsu discloses in Figure 16 a block of a 3D NAND flash memory array that includes multiple groups of pages. Each page group contains multiple cell strings, each cell string has a channel, and each string includes a drain select gate and a source select gate, para. 109-113. The drain select gates in page group 1600a are connected to the control signal SG[0], para. 110. Therefore, two strings in page group 1600a can corresponding to the claimed first and second plugs. See Fig. 18: step 1801a, supplying VDD to all bit lines and pulsing all selects gates SG[0:n] of all the page groups to load VDD into all the channels of all the cell strings in each page group, para. 119. Thus, the channels of two strings under SG[0] are precharged to VDD];
precharging a third channel of a third plug and a fourth channel of a fourth plug, wherein the third channel and the fourth channel correspond to a second select line [the drain select gates in page group 1600b are connected to the second control signal SG[1], para. 110. Therefore, two strings in page group 1600b can corresponding to the claimed third and fourth plugs. See Fig. 18: step 1801a, supplying VDD to all bit lines and pulsing all selects gates SG[0:n] of all the page groups to load VDD into all the channels of all the cell strings in each page group, para. 119. Thus, the channels of two string under SG[1] are precharged to VDD];
applying a program-enable voltage to each of the first channel, the second channel, the third channel, and the fourth channel [see Fig. 18: step 1801c, applying PAGE 0 data to the bit lines and pulsing the first select gate SG[0] to load the data into the channels of the cell strings in the first page group 1600a. The bit lines with 0V (data 0) will discharge the channels of the associated strings to 0V, para 122. After PAGE 0 is loaded and programming has begun, the select gate SG[0] is turned off. The data for the next page (PAGE 1) is applied to the bit lines, and the next select gate (e.g., SG[1] associated with the page group 1) is pulsed to load the data to (Channel 1 [0:k]) and begin programming that page, para. 124];
simultaneously programming memory cells included in the first plug, the second plug, the third plug, and the fourth plug [PAGE 0 in page group 1600a, PAGE 1 in page group 1600b and other pages up to PAGE N in page group 1600c can be loaded with different data and programmed simultaneously by applying 20V to the word line (e.g., WL[c]) that connects them together, para. 110. See Fig. 18: step 1801d, after the data for multiple pages are loaded and programming has begun, the voltages of the word lines will be maintained to allow all the pages (0 to N) to continue programming in parallel and the cells in the multiple selected pages complete their programming operation in parallel, para. 126].
Regarding claim 16, Hsu discloses where programming the selected memory cells comprises:
applying a pass voltage to unselected word lines among word lines coupled in common to the first plug, the second plug, the third plug, and the fourth plug [see Fig. 18, all the unselected word lines (such as WL[1:c−1] through WL[c+1:m] for example) are supplied with a middle-high inhibit voltage (Vinh), such as 8V to 10V, para. 120]; and
applying a program voltage to a selected word line among the word lines [see Fig.18, the selected word line (such as WL[c] for example) is supplied with the program high voltage (Vpgm), such as 15V to 20V, para. 120].
Regarding independent claim 21, Hsu discloses a method of operating a memory device [see Fig. 18, showing exemplary programming operations to program the 3D NAND flash memory block shown in FIG. 16], the method comprising:
simultaneously precharging a plurality of first cell strings coupled to a first select line and a plurality of second cell strings coupled to a second select line [Hsu discloses in Figure 16 a block of a 3D NAND flash memory array that includes multiple groups of pages. Each page group contains multiple cell strings, each cell string has a channel, and each string includes a drain select gate and a source select gate, para. 109-113. A string in page group 1600a may be treated as the claimed first plug and a string in page group 1600b may be treated as the claimed second plug. The drain select gates in page group 1600a are connected to the control signal SG[0], the drain select gates in page group 1600b are connected to SG[1], para. 110. See Fig. 18: step 1801a, supplying VDD to all bit lines and pulsing all selects gates SG[0:n] of all the page groups to load VDD into all the channels of all the cell strings in each page group, para. 119.;
simultaneously programming memory cells included in the plurality of first cell strings and the plurality of second cell strings [PAGE 0 in page group 1600a, PAGE 1 in page group 1600b and other pages up to PAGE N in page group 1600c can be loaded with different data and programmed simultaneously by applying 20V to the word line (e.g., WL[c]) that connects them together, para. 110. See Fig. 18: step 1801d, after the data for multiple pages are loaded and programming has begun, the voltages of the word lines will be maintained to allow all the pages (0 to N) to continue programming in parallel and the cells in the multiple selected pages complete their programming operation in parallel, para. 126].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 20190147959) as applied to claims 1 and 12 above, in view of Choi et al. (US 20020114187).
Regarding claim 3, Hsu teaches the limitations with respect to claim 1.
Furthermore, Hsu discloses wherein precharging the first channel and the second channel comprises:
applying a precharge voltage to a first bit line coupled to the first plug [see Fig. 18: step 1801a, all the bit lines BL[0:k] are supplied with VDD (data 1), and all the select gates SG[0:n] of all the page groups are pulsed to load VDD into all the channels of all the cell strings in each page group, para. 119];
applying the precharge voltage to a second bit line coupled to the second plug [see Fig. 18: step 1801a, all the bit lines BL[0:k] are supplied with VDD (data 1), and all the select gates SG[0:n] of all the page groups are pulsed to load VDD into all the channels of all the cell strings in each page group, para. 119];
turning on a first select transistor between the first channel and the first bit line [the drain select gates in page group 1600a are connected to the control signal SG[0] and their drains are connected to the bit lines BL[0:k], para. 110. All the select gates SG[0:n] of all the page groups are pulsed to load VDD into all the channels of all the cell strings in each page group, para. 119];
and turning on a second select transistor between the second channel and the second bit line [the drain select gates in page group 1600b are connected to SG[1] and their drains are connected to the bit lines BL[0:k], para. 110. All the select gates SG[0:n] of all the page groups are pulsed to load VDD into all the channels of all the cell strings in each page group, para. 119].
However, Hsu is silent with respect to applying a pass voltage to word lines coupled in common to the first plug and the second plug.
Choi et al. teach applying a pass voltage to word lines to activate the cell string channels before a bit line precharge interval [see Fig. 5, para. 64-66].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Choi et al. to the teachings of Hsu such that applying Choi et al.’s pass voltage to Hsu’s common word lines during precharge operation. The combination would ensure the memory cells along the first and second strings are conductive so that the VDD voltage is reliably transferred into both channels, thereby providing an initial channel voltage and reducing program disturbance.
Regarding claim 4, Hsu in combination with Choi et al. teaches the limitations with respect to claim 1.
Furthermore, Hsu discloses wherein the precharge voltage is a voltage higher than 0 V [VDD is approximately from 3V to 5V, para. 79].
Regarding claim 5, Hsu in combination with Choi et al. teaches the limitations with respect to claim 1.
Furthermore, Hsu discloses wherein:
turning on the first select transistor comprises applying a turn-on voltage to the first select line coupled to a gate of the first select transistor [the drain select gates in page group 1600a are connected to the control signal SG[0] and their drains are connected to the bit lines BL[0:k], para. 110. A selected drain select gate (e.g., SG[0]) is turned on to load the bit line data into the channel regions of the NAND cell strings of the selected page group, para. 113], and
turning on the second select transistor comprises applying the turn-on voltage to the second select line coupled to a gate of the second select transistor [the drain select gates in page group 1600b are connected to SG[1] and their drains are connected to the bit lines BL[0:k], para. 110. The next select gate (e.g., SG[1] associated with the page group 1) is pulsed to load the data to (Channel 1 [0:k]), para. 124].
Regarding claim 13, Hsu teaches the limitations with respect to claim 12.
Furthermore, Hsu discloses wherein precharging the first channel, the second channel, the third channel, and the fourth channel comprises:
applying a precharge voltage to a first bit line coupled to the first plug [see Fig. 18: step 1801a, all the bit lines BL[0:k] are supplied with VDD (data 1), and all the select gates SG[0:n] of all the page groups are pulsed to load VDD into all the channels of all the cell strings in each page group, para. 119];
applying the precharge voltage to a second bit line coupled to the second plug [see Fig. 18: step 1801a, all the bit lines BL[0:k] are supplied with VDD (data 1), and all the select gates SG[0:n] of all the page groups are pulsed to load VDD into all the channels of all the cell strings in each page group, para. 119];
applying the precharge voltage to a third bit line coupled to the third plug [see Fig. 18: step 1801a, all the bit lines BL[0:k] are supplied with VDD (data 1), and all the select gates SG[0:n] of all the page groups are pulsed to load VDD into all the channels of all the cell strings in each page group, para. 119];
applying the precharge voltage to a fourth bit line coupled to the fourth plug [see Fig. 18: step 1801a, all the bit lines BL[0:k] are supplied with VDD (data 1), and all the select gates SG[0:n] of all the page groups are pulsed to load VDD into all the channels of all the cell strings in each page group, para. 119];
simultaneously turning on a first select transistor between the first channel and the first bit line and a second select transistor between the second channel and the second bit line [the drain select gates in page group 1600a are connected to the control signal SG[0] and their drains are connected to the bit lines BL[0:k], para. 110. All the select gates SG[0:n] of all the page groups are pulsed to load VDD into all the channels of all the cell strings in each page group, para. 119]; and
simultaneously turning on a third select transistor between the third channel and the third bit line and a fourth select transistor between the fourth channel and the fourth bit line [the drain select gates in page group 1600b are connected to SG[1] and their drains are connected to the bit lines BL[0:k], para. 110. All the select gates SG[0:n] of all the page groups are pulsed to load VDD into all the channels of all the cell strings in each page group, para. 119].
However, Hsu is silent with respect to applying a pass voltage to word lines coupled in common to the first plug, the second plug, the third plug, and the fourth plug.
Choi et al. teach applying a pass voltage to word lines to activate the cell string channels before a bit line precharge interval [see Fig. 5, para. 64-66].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Choi et al. to the teachings of Hsu such that applying Choi et al.’s pass voltage to Hsu’s common word lines during precharge operation. The combination would ensure the memory cells along the first and second strings are conductive so that the VDD voltage is reliably transferred into both channels, thereby providing an initial channel voltage and reducing program disturbance.
Regarding claim 14, Hsu in combination with Choi et al. teaches the limitations with respect to claim 13.
Furthermore, Hsu discloses wherein:
simultaneously turning on the first select transistor and the second select transistor comprises applying a turn-on voltage to the first select line coupled in common to gates of the first select transistor and the second select transistor [the drain select gates in page group 1600a are connected to the control signal SG[0] and their drains are connected to the bit lines BL[0:k], para. 110. A selected drain select gate (e.g., SG[0]) is turned on to load the bit line data into the channel regions of the NAND cell strings of the selected page group, para. 113], and
simultaneously turning on the third select transistor and the fourth select transistor comprises applying the turn-on voltage to the second select line coupled in common to gates of the third select transistor and the fourth select transistor [the drain select gates in page group 1600b are connected to SG[1] and their drains are connected to the bit lines BL[0:k], para. 110. The next select gate (e.g., SG[1] associated with the page group 1) is pulsed to load the data to (Channel 1 [0:k]), para. 124].
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 20190147959) as applied to claim 12 above, in view of Park (US 20120268996).
Regarding claim 15, Hsu teaches the limitations with respect to claim 12.
Furthermore, Hsu discloses wherein applying the program-enable voltage to each of the first channel, the second channel, the third channel, and the fourth channel comprises:
inputting data to each of a first page buffer, a second page buffer, a third page buffer, and a fourth page buffer coupled to the first plug, the second plug, the third plug, and the fourth plug through a first bit line, a second bit line, a third bit line, and a fourth bit line, respectively; and
outputting, the program-enable voltage to the first bit line, the second bit line, the third bit line, and the fourth bit line, respectively, depending on the data [a selected bit line BL0-BLk can be applied with a 0V or VDD signal from the page buffer 606, para. 67. See Fig. 18: step 1801c, applying PAGE 0 data to the bit lines and pulsing the first select gate SG[0] to load the data into the channels of the cell strings in the first page group 1600a. The bit lines with 0V (data 0) will discharge the channels of the associated strings to 0V. The cells on PAGE 0 with 0V channel voltage, the electric field between the cells' gate and their channel (which is 0V) will cause electrons to inject from their channel to the charge storage element of the cells and begin programming, para 122. After PAGE 0 is loaded and programming has begun, the select gate SG[0] is turned off. The data for the next page (PAGE 1) is applied to the bit lines, and the next select gate (e.g., SG[1] associated with the page group 1) is pulsed to load the data to (Channel 1 [0:k]) and begin programming that page, para. 124].
However, Hsu is silent with respect to inputting data to each of a first page buffer, a second page buffer, a third page buffer, and a fourth page buffer coupled to the first plug, the second plug, the third plug, and the fourth plug through a first bit line, a second bit line, a third bit line, and a fourth bit line, respectively; and outputting, by the first page buffer, the second page buffer, the third page buffer, and the fourth page buffer, the program-enable voltage to the first bit line, the second bit line, the third bit line, and the fourth bit line, respectively, depending on the data.
Park teaches inputting data to each of a first page buffer, a second page buffer, a third page buffer, and a fourth page buffer [see Fig. 1, when the external data DATA is transferred to the page buffers PB1 to PBk of the page buffer group 150, the page buffers PB1 to PBk store the external data in their internal latch circuits, para. 32] coupled to the first plug, the second plug, the third plug, and the fourth plug through a first bit line, a second bit line, a third bit line, and a fourth bit line, respectively [see Fig. 2, the strings STe1 to STek are coupled to the respective bit lines BLe1 to BLek, para. 20. See Fig. 3, the page buffer group 150 includes the plurality of page buffers PB1 to PBk coupled to the bit lines BLe1 to BLek, para. 27]; and outputting, by the first page buffer, the second page buffer, the third page buffer, and the fourth page buffer, the program-enable voltage to the first bit line, the second bit line, the third bit line, and the fourth bit line, respectively, depending on the data [the page buffers PB1 to PBk selectively precharge the bit lines BLe1 to BLek depending on received data in order to store data in the memory cells C0e1 to C0ek, para. 27. The latch circuit of the page buffer supplied either the program inhibition voltage or the program permission voltage to a corresponding bit line, depending on data received in a program operation, para. 48].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Park to the teachings of Hsu such that implementing Hsu’s data dependent bit line biasing using plurality of page buffers that storing respective program data and supplying a program inhibition voltage or the program permission voltage to corresponding bit lines as taught by Park, thereby the modification would allow to control Hsu’s four strings channels based upon their respective data while maintaining Hsu’s multi page programming operation.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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