DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 05/11/2026 is acknowledged.
Claims 19 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/11/2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “ a sampling circuit coupled between the sensing circuit and the processing circuit” in Claim 2, the “sampling circuit having a….control terminal” in Claim 11 must be shown or the feature(s) canceled from the claim(s). Fig. 2A discloses a current sensing circuit comprising a processing circuit which further comprises a sampling circuit. However Fig. 2A fails to show a sampling circuit coupled between a current sensing circuit. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 10-18 is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Sung et al. “Mixed-Mode Chip Implementation of Digital Space SVPWMWithSimplified-CPU and 12-Bit 2.56 Ms/s Switched-Current Delta-Sigma ADC in Motor Drive”, 2012, hereinafter ‘Sung’.
Regarding Claim 1, Sung discloses an apparatus comprising: a driver circuit having a driver output, the driver circuit including a pulse width modulation (PWM) circuit (Fig. 1, PWM) configured to provide a PWM signal at the driver output at a frequency (Fig. 1, PWM); a sensing circuit having a sense input and a sense output (Fig. 2, hall effect sensor with input of driving current and output of analog current signal); and a processing circuit having a processing input and a processing output, the processing input coupled to the sense output (Fig. 2, Delta Sigma ADC input from Hall effect sensor and output of digital voltage signals to CPU; Delta Sigma ADC include modulator/decimator filter), the processing circuit including a filter having zeros at the frequency and multiples of the frequency (Fig. 10, decimator filter comprising COMB filter, FIR1, FIR2 with frequency rates of 16, 2, 2 per Page 922 first paragraph).
Regarding Claim 2, Sung further discloses wherein the frequency is a first frequency (Fig. 10, decimator filter comprising COMB filter, FIR1, FIR2 with frequency rates of 16, 2, 2 per Page 922 first paragraph), and the apparatus further comprises a sampling circuit (Fig. 2, delta sigma ADC) coupled between the sensing circuit (Fig. 2, hall effect sensor) and the processing circuit (Fig. 2, delta sigma ADC with a filter; The second order delta sigma (Δ-Σ) ADC, which includes both modulator and decimator filter, converts the analog current signal that is sensed by the Hall sensor into the digital voltage signal Page 917), the sampling circuit configured to provide samples at a second frequency (Figs. 8 and 9; Page 921, first paragraph; Page 922, first paragraph).
Regarding Claim 3, Sung further discloses wherein the first frequency is an integer multiple of the second frequency (Page 922 frequency rates of 16, 2, 2).
Regarding Claim 4, Sung further discloses wherein the filter includes a comb section and an integrator section, the comb section configured to operate at a third frequency, and the integrator section configured to operate at the second frequency (Fig. 10).
Regarding Claim 5, Sung further discloses wherein the filter implements a sinc function (Fig. 10, FIR filters; known in the art in digital signal processing, the ideal impulse response of a perfect low-pass FIR filter is a sinc function).
Regarding Claim 6, Sung further discloses wherein the sampling circuit includes a sigma-delta analog to digital converter (ADC) having a quantizer configured to provide the samples at the third frequency, the third frequency being related to the second frequency by an oversampling ratio (Abstract disclosing oversampling ratio; Page 916 last paragraph disclosing oversampling ADC; Fig. 2, delta sigma ADC comprises modulator; Fig. 12 delta sigma modulator having quantizer).
Regarding Claim 7, Sung further discloses wherein the sampling circuit includes a successive approximation ADC (Page 917, last paragraph disclosing 8 bit sampling rate).
Regarding Claim 8, Sung further discloses wherein the sense input is coupled to a battery terminal or a motor terminal (Fig. 2, sensor coupled to IM motor).
Regarding Claim 10, Sung further discloses wherein the filter is a digital filter (Page 921, disclosing decimator as digital filter).
Regarding Claim 11, Sung discloses a system comprising: a device (Fig. 2, IM motor); a sampling circuit having a sampling input, a sampling output, and a control terminal, the sampling input coupled to the device (Fig. 2, hall effect sensor with input of driving current and output of analog current signal); a driver circuit having a driver output coupled to the control terminal of the sampling circuit, the driver circuit including a pulse width modulation (PWM) circuit (Fig. 1, PWM) configured to provide a PWM signal at the driver output at a frequency (Fig. 1, PWM); a sensing circuit having a sense input and a sense output, the sense input coupled to the sampling output (Fig. 2, hall effect sensor with input of driving current and output of analog current signal); and a processing circuit having a processing input and a processing output, the processing input coupled to the sense output (Fig. 2, Delta Sigma ADC input from Hall effect sensor and output of digital voltage signals to CPU; Delta Sigma ADC include modulator/decimator filter), the processing circuit including a filter having zeros at the frequency and multiples of the frequency (Fig. 10, decimator filter comprising COMB filter, FIR1, FIR2 with frequency rates of 16, 2, 2 per Page 922 first paragraph).
Regarding Claim 12, Sung further discloses wherein the device Includes a battery or a motor device (Fig. 2, IM motor).
Regarding Claim 13, Sung further discloses wherein the frequency is a first frequency, and the sampling circuit is configured to provide samples at a second frequency, and the filter is configured to provide a filtered version of the samples at the second frequency (Figs. 8 and 9; Page 921, first paragraph; Page 922, first paragraph; Fig. 10).
Regarding Claim 14, Sung further discloses wherein the first frequency is an integer multiple of the second frequency (Page 922 frequency rates of 16, 2, 2).
Regarding Claim 15, Sung further discloses wherein the filter includes at least one of an analog filter or a digital filter (Page 921, disclosing decimator as digital filter).
Regarding Claim 16, Sung further discloses wherein the filter includes a comb section with a downconverter and an integrator section, the comb section configured to operate at a third frequency, and the integrator section configured to operate at the second frequency (Fig. 10, Page 922, filters having a down rate).
Regarding Claim 17, Sung further discloses wherein the sampling circuit includes a sigma-delta analog to digital converter (ADC) having a quantizer configured to provide the samples at the third frequency, the third frequency being related to the second frequency by an oversampling ratio (Abstract disclosing oversampling ratio; Page 916 last paragraph disclosing oversampling ADC; Fig. 2, delta sigma ADC comprises modulator; Fig. 12 delta sigma modulator having quantizer).
Regarding Claim 18, Sung further discloses wherein the sampling circuit includes a successive approximation register (SAR) ADC (Page 917, last paragraph disclosing 8 bit sampling rate).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sung et al. “Mixed-Mode Chip Implementation of Digital Space SVPWMWithSimplified-CPU and 12-Bit 2.56 Ms/s Switched-Current Delta-Sigma ADC in Motor Drive”, 2012, hereinafter ‘Sung’ as applied to claim 1 above, and further in view of Martinez Perez et al. (US 20210028691), hereinafter ‘Martinez Perez’.
Regarding Claim 9, Sung fails to explicitly disclose wherein the filter is an analog filter.
Martinez Perez discloses an on board charger comprising an analog filter coupled to sensing device, PWM controller, A/D and PI controller for the benefit of locally enhancing the current ripple of the output current, at the sensing feedback from current sensor and generating a filtered version of the sensed value of the output current in which component of the sensed value of the output current is relatively enhanced (Para [0047-0048]).
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date to combine and provide the filter as an analog filter for the benefit of locally enhancing the current ripple of the output current, at the sensing feedback from current sensor and generating a filtered version of the sensed value of the output current in which component of the sensed value of the output current is relatively enhanced as taught by Martinez Perez in Para [0047-0048].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALESA ALLGOOD whose telephone number is (571)270-5811. The examiner can normally be reached M-F 7:30 AM-3:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eman Alkafawi can be reached at (571) 272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALESA ALLGOOD/ Primary Examiner, Art Unit 2858
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