DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Election/Restrictions 3
III. Claim Rejections - 35 USC § 112 3
A. Claims 1-13 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. 3
1. Claim 1 3
2. Claim 4 4
3. Claim 8 4
4. Claim 9 4
IV. Claim Rejections - 35 USC § 102 5
A. Claims 1-9, 12, and 13 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2019/0341323 (“Nishimura”). 5
V. Claim Rejections - 35 USC § 103 9
A. Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Nishimura in view of US 20200402901 (“Yasutake”). 9
VI. Pertinent Prior Art 13
Conclusion 13
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Election/Restrictions
Applicant’s election of invention group I, species group A, directed to embodiment A10, claims 1-13, in the reply filed on 08/21/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
III. Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
A. Claims 1-13 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
1. Claim 1
Claim 1 recites the limitations “a first side in the thickness direction” in line 3 and “a second side in the thickness direction” in line 12. While the “thickness direction” is clear given that the specification states that it is the Z direction, it is not clear as to what element the “first side” and “second side” refers. Is the element the lead 1 or the resin 4 or the semiconductor element 3 or the semiconductor device, itself? As such, the metes and bounds of the claim are unclear.
The limitation, “the second side in the thickness direction” is also recited one or more times in each of claims 3, 5, 7, and 10 and is unclear for the same reasons.
Claims 2-13 are rejected for including the same indefinite feature by depending from claim 1, either directly or indirectly and for claims 3, 5, 7, and 10 reciting the unclear limitation.
2. Claim 4
Claim 4 recites the limitation, “another one of the first side surfaces”. There is insufficient antecedent basis for this limitation in the claim.
3. Claim 8
Claim 8 recites the limitation, “another one of the second side surfaces”. There is insufficient antecedent basis for this limitation in the claim.
4. Claim 9
The limitation, “the first side and the second side in the first direction” in line 6 and “the first side and the second side in the second direction” in line 15. As explained under claim 1, it is not clear as to what element the “first side” and “second side” refers. Is the element the lead 1 or the terminal sections 21, 22 or the resin 4 or the semiconductor element 3 or the semiconductor device A10, itself? As such, the metes and bounds of the claim are unclear.
For the purposes of examination, the claims will be interpreted as best understood in light of the figures.
IV. Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
A. Claims 1-9, 12, and 13 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2019/0341323 (“Nishimura”).
The fifth embodiment of the semiconductor device A50, shown in Figs. 42-48 (¶ 149) of Nishimura, includes a modification shown in Fig. 65 (¶ 197), which reads on the following claims, so the discussion in the specification directed to Figs. 42-48 applies to the modification shown in Fig. 65.
With regard to claims 1-9, Nishimura discloses, generally in Figs. 1, 2, and 65,
1. A semiconductor device [QFN A50 in Fig. 65 (¶ 194)] comprising:
[1] a lead 20/30 [¶¶ 85, 87] including a main section that includes an obverse surface [top surface of lead 20/30] facing a first side [assumed top side of semiconductor device] in a thickness direction Z;
[2] a semiconductor element 41 [¶ 76] supported by the obverse surface [as shown in Figs. 2 and 65]; and
[3] a sealing resin 60 [¶ 76] covering a portion of the lead 20/30 and the semiconductor element 41,
wherein
[4] the lead 20/30 includes a base member 20(=23/24/25) [¶¶ 85, 161-163, 197] and a metal layer 30(=35/36) [¶¶ 87, 171, 197] covering a portion of the base member 20,
[5] the lead 20/30 includes a plurality of first terminal sections 24/25/35/36 aligned in a first direction Y perpendicular to the thickness direction Z [as shown in Figs. 1 and 2,
[6a] each of the plurality of first terminal sections 24/25/35/36 includes
[6b] a first mounting surface [bottom surface of 35] facing a second side [bottom side of semiconductor device] in the thickness direction Z [¶ 87: “The second electrodes 30 are terminals used for mounting the semiconductor device …”], and
[6c] a first side surface [side surface of 36] facing in a second direction X perpendicular to the thickness direction and the first direction Y,
[7] the first mounting surface [bottom surface of 35 and side surface of 36] and the first side surface [side surface of 36] are exposed from the sealing resin 60, and
[8] the first mounting surface [bottom surface of 35 and side surface of 36] and the first side surface are entirely formed of the metal layer 30.
2. The semiconductor device according to claim 1, wherein
[1] the sealing resin 60 includes a first resin side surface 631 located at an end in the second direction X and facing in the second direction X, and
[2] the first side surface [side surface of 36] is located inward of the sealing resin 60 from the first resin side surface 631 as viewed in the thickness direction Z [as shown in Fig. 65].
3. The semiconductor device according to claim 2, wherein
[1] the sealing resin 60 includes a first resin intermediate surface 632b [¶ 177] connected to an end of the first resin side surface 631 [¶ 167] on the second side in the thickness direction Z, and
[2] the first resin intermediate surface 632b faces the second side [assumed bottom surface of semiconductor device A50] in the thickness direction Z and is located between the first side surface [side surface of 36] and the first resin side surface 631 in the second direction X.
4. The semiconductor device according to claim 1, wherein the first side surface [side surface of 36] is connected to the first mounting surface [bottom surface of 35] and flush with another one of the first side surfaces [side surface of 36] [as shown in Figs. 3 and 65].
5. The semiconductor device according to claim 1, wherein
[1] the lead includes a plurality of second terminal sections 24/25/35/36 aligned in the second direction X [as shown in Figs. 1-3, but configured as shown in Fig. 65],
[2a] each of the plurality of second terminal sections 24/25/35/36 includes
[2b] a second mounting surface [bottom surface of 35] facing the second side [assumed bottom surface of semiconductor device A50] in the thickness direction Z, and
[2c] a second side surface [side surface of 36] facing in the first direction Y,
[3] the second mounting surface [bottom surface of 35] and the second side surface [side surface of 36] are exposed from the sealing resin 60, and
[4] the second mounting surface [bottom surface of 35] and the second side surface [side surface of 36] are entirely formed of the metal layer 30.
6. The semiconductor device according to claim 5, wherein
[1] the sealing resin includes a second resin side surface 631 located at an end in the first direction Y and facing in the first direction Y [as shown in Figs. 1-3 and 65], and
[2] the second side surface [side surface of 36] is located inward of the sealing resin 60 from the second resin side surface 631 as viewed in the thickness direction Z [as shown in Figs. 1-3 and 65].
7. The semiconductor device according to claim 6, wherein
[1] the sealing resin 60 includes a second resin intermediate surface 632b connected to an end of the second resin side surface 631 on the second side [assumed bottom side of the semiconductor device A50] in the thickness direction Z, and
[2] the second resin intermediate surface 632b faces the second side [assumed bottom side of the semiconductor device A50] in the thickness direction Z and is located between the second side surface [side surface of 36] and the second resin side surface 631 in the first direction Y [as shown in Figs. 1-3 and 65].
8. The semiconductor device according to claim 5, wherein the second side surface [side surface of 36] is connected to the second mounting surface [bottom surface of 35] and flush with another one of the second side surfaces [side surface of 36] [as shown in Figs. 1-3 and 65].
9. The semiconductor device according to claim 5, wherein
[1] the plurality of first terminal sections 24/25/35/36 are aligned at ends of the sealing resin 60 on a first side and a second side in the second direction X as viewed in the thickness direction Z [as shown in Figs. 1, 3, and 65],
[2] the plurality of second terminal sections 24/25/35/36 are aligned at ends of the sealing resin 60 on a first side and a second side in the first direction Y as viewed in the thickness direction Z [as shown in Figs. 1 and 3],
[3] each of the plurality of first terminal sections 24/25/35/36 includes two first inner surfaces connected to one of the first mounting surfaces [bottom surface of 35] and one of the first side surfaces [side surface of 36], the two first inner surfaces facing the first side and the second side in the first direction Y, respectively, [as shown in Figs. 1-3 and 65]
[4] each of the plurality of second terminal sections 24/25/35/36 includes two second inner surfaces connected to one of the second mounting surfaces [bottom surface of 35] and one of the second side surfaces [side surface of 36], the two second inner surfaces facing the first side and the second side in the second direction X, respectively, [as shown in Figs. 1-3 and 65]and
[5] the first inner surfaces and the second inner surfaces are covered with the sealing resin 60 [as shown in Figs. 1 and 3].
Bearing in mind the rejection of claim 9 under 35 USC 112(b), the claimed “inner surfaces” in Nishimura are considered in the context of the inner surfaces 213 shown in Fig. 15 of the Instant Application.
With regard to claims 12-13, Nishimura further discloses ,
12. The semiconductor device according to claim 1, wherein
[1] the main section [of the lead 20] is connected to at least one of the plurality of first terminal sections 24/25/35/36, and
[2] the semiconductor element 41 includes a plurality of electrodes 42 [¶ 92] arranged on a side opposite from the obverse surface [of the lead 20] in the thickness direction Z and connected to the obverse surface [of the lead 20] [as shown in Fig. 65].
13. The semiconductor device according to claim 1, wherein the metal layer 30 comprises a plating layer [¶¶ 87, 171, i.e. electrolessly-plated Ni/Pd/Au].
V. Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Nishimura in view of US 20200402901 (“Yasutake”).
Claims 10 and 11 read,
10. The semiconductor device according to claim 9, wherein
[1] the lead includes a third terminal section arranged at a position closer to an end of the sealing resin than the plurality of first terminal sections in the first direction and closer to an end of the sealing resin than the plurality of second terminal sections in the second direction,
[2a] the third terminal section includes
[2b] a third mounting surface facing the second side in the thickness direction,
[2c] a third side surface facing a same side as the first side surface, and
[2d] a fourth side surface facing a same side as the second side surface,
[3] the third mounting surface, the third side surface, and the fourth side surface are exposed from the sealing resin, and
[4] the third mounting surface, the third side surface, and the fourth side surface are entirely formed of the metal layer.
11. The semiconductor device according to claim 10, wherein
[1] the sealing resin has a rectangular shape extending in the first direction and the second direction as viewed in the thickness direction, and
[2] the third terminal section comprises a plurality of third terminal sections each arranged at one of four corners of the sealing resin as viewed in the thickness direction.
The prior art of Nishimura, as explained above, discloses each of the features of claims 1, 5, and 9.
Nishimura does not disclose the claimed “third terminals” at the four corners of the semiconductor device A50 and does not, consequently, disclose the limitations of claims 10 and 11.
Yasutake, like Nishimura, teaches a semiconductor device in, e.g., Figs. 1-6 including a semiconductor element 3 mounted on the main surface 111 of the first lead 1 (Yatsutake: ¶ 46) and encapsulated in a sealing resin 5 (Yasutake: ¶¶ 48-50). Also like Nishimura, Yatsutake teaches (1) that the lead 1/2 has a plurality of terminal portions 2 exposed at the at each of the four sides of the semiconductor device and the bottom surface, i.e. the mounting surface, as shown in Figs. 2 and 4, and (2) that a “surface coating layer (not shown) is formed on all parts of the first lead 1 that are exposed from the sealing layer 5” (¶ 36) with a metal, e.g. Au, that has solder wettability to form a “surface coating layer” (id.).
Still further, each of Nishimura and Yatsutake teach that the semiconductor device may include a heat dissipation element to remove heat from the semiconductor element. In this regard, Nishimura includes “heat dissipating layer 70” made of the same material and at the same time as the leads 20/30 (Nishimura: ¶¶ 120-132; Figs. 29-35). Nishimura does not show the heat dissipation layer 70 in the embodiment in Fig. 65 but states that it may be provided in other embodiments (Nishimura: ¶ 143 and ¶ 202-206; Fig. 67).
Similarly, Yasutake states that the mounting portion 110 of the first lead 1 functions as a heat dissipating element (Yasutake: ¶¶ 32, 61-65). Yatsutake further teaches that the first lead 1 of the lead 1/2 includes leads 120 at each of the four corners that are connected by connection portions 130 to the mounting portion 110. Yasutake further explains that the corner leads 120 function to transfer heat from the mounting portion 110 to the circuit board (Yasutake: ¶¶ 61-65).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the heat dissipating layer 70 of Nishimura in the embodiment shown in Fig. 65, because Nishimura states that other embodiments can include a heat dissipating layer 70 (Nishimura: Figs. 29, 30; ¶ 143 and ¶ 202-206; Fig. 67).
In addition, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the four corner leads, each connected to the heat dissipating layer 70 by a respective connecting portion, in order to further aid in the heat removal that would otherwise be provided by the heat dissipating layer 70 alone, as taught in Yasutake (Yasutake: ¶¶ 61-65). As such, Yasutake may bee seen as an improvement to Nishimura in this aspect. (See MPEP 2143.)
So modified, Nishimura modified to have the four corner leads/connecting portions taught in Yasutake teaches all of the limitations of claim 10 and 11, as follows:
10. The semiconductor device according to claim 9, wherein
[1] the lead [20/30 of Nishimura] includes a third terminal section [120/130 of Yasutake used in Nishimura] arranged at a position closer to an end of the sealing resin [61 of Nishimura] than the plurality of first terminal sections [24/25/35/36 of Nishimura] in the first direction [Y in Nishimura] and closer to an end of the sealing resin [61 of Nishimura] than the plurality of second terminal sections [24/25/35/36 ] in the second direction [X in Nishimura],
[2a] the third terminal section [120/130 of Yasutake used in Nishimura] includes
[2b] a third mounting surface [i.e. bottom surface 122 of 120 of Yasutake used in Nishimura] facing the second side [assumed bottom side of semiconductor device A50 in Nishimura] in the thickness direction [Z in Nishimura],
[2c] a third side surface [123 of 120 of Yasutake (¶ 34; Figs. 2, 3) used in Nishimura] facing a same side as the first side surface [side surface of 36 in Nishimura], and
[2d] a fourth side surface [123 of 120 of Yasutake (¶ 34; Figs. 2, 3) used in Nishimura] facing a same side as the second side surface [side surface of 36 in Nishimura],
[3] the third mounting surface, the third side surface, and the fourth side surface are exposed from the sealing resin [61 of Nishimura, as shown also in Figs. 2, 3, 5, and 6 of Yasutake], and
[4] the third mounting surface, the third side surface, and the fourth side surface are entirely formed of the metal layer [30 of Nishimura because the leads are exposed before the plating, as taught in each of Nishimura and Yasutake (supra)].
11. The semiconductor device according to claim 10, wherein
[1] the sealing resin [61 of Nishimura and 5 in Yasutake] has a rectangular shape extending in the first direction Y and the second direction X as viewed in the thickness direction Z, and
[2] the third terminal section [120/130 of Yasutake used in Nishimura] comprises a plurality of third terminal sections each arranged at one of four corners of the sealing resin as viewed in the thickness direction Z [as shown in Figs. 2, 3, 5, and 6 of Yasutake].
This is all of the limitations of claims 10 and 11.
VI. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Each of the following references is cited for disclosing all of the limitations of at least claim 1:
US 2021/0098374 (“Yanagida”): See Figs. 1-4 and associated text.
US 2017/0256509 (“Lee”): See at least Fig. 8 and associated text.
US 2008/0246132 (“Kasuya”): See Figs. 1A through 3 and associated text.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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