DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 7-10, 12 and 22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species (B and C) Modification (C2) and Embodiment (II and III), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 20 August 2026.
Applicant’s election without traverse of Species A, Modification C1 and Embodiment I in the reply filed on 20 August 2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 29 May 2024 has been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 11 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 11 is dependent upon claim 9 which has been withdrawn from consideration for being directed to a non-elected species (B, C, C2, II and II) in the restriction requirement set forth on 6 July 2026
Applicant may cancel the claim, amend the claim to place the claim in proper dependent form, rewrite the claim in independent form, or present a sufficient showing that the dependent claim complies with the statutory requirements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1-2, 5, 11, 13 and 15 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by Rabiul Islam et al. (2021/0225824 A1; hereinafter “Islam”).
Regarding Claim 1, Islam teaches a semiconductor package comprising:
a package substrate (300, Fig. 3, para [0031] describes a package component 300 which may be a package substrate);
a connection substrate mounted on the package substrate (CS, annotated Fig. 3 depicts a connection substrate CS mounted on the package substrate 300 wherein para [0024] describes the connection substrate CS comprises an insulating material 110 and through vias 112A), the connection substrate including a first conductive connection structure (112A, Fig. 1J and annotated Fig. 3, para [0026] describes through vias 112A comprising a conductive connection structure included in the connection substrate CS);
a first integrated circuit device mounted on the package substrate (108, Fig. 3, para [0022] describes a second semiconductor die 108, herein a first integrated circuit device, mounted on the package substrate 300 through conductive terminals 114); and
a second integrated circuit device disposed on the connection substrate and the first integrated circuit device (106, annotated Fig. 3, para [0018] describes a first semiconductor die, herein a second integrated circuit device, disposed on the connection substrate CS and the first integrated circuit device 108), the second integrated circuit device including a first portion overlapping the first integrated circuit device (FP, annotated Fig. 3 depicts a first portion FP of the second integrated circuit 106 device overlapping the first integrated circuit device 108) and a second portion overlapping the connection substrate (SP, annotated Fig. 3 depicts a second portion SP of the second integrated circuit 106 device overlapping the connection substrate CS),
wherein one of the first integrated circuit device and the second integrated circuit device comprises a photonic integrated circuit device (108, Fig. 3, para [0020] describes wherein the first integrated circuit 108 may be a photonic die) to which an optical fiber is attached (108 and 304, Fig. 3, para [0034] describes an optical fiber 304 attached to side surfaces of the first integrated circuit device 108), and the other of the first integrated circuit device and the second integrated circuit device comprises an electronic integrated circuit device (106, Fig. 3, para [0018] describes wherein the second integrated circuit device 106 may be an electronic die including electronic devices), and
wherein the second integrated circuit device is electrically connected to the package substrate via the first conductive connection structure of the connection substrate (106, 106B, 112A, 300B and CS, Fig. 1J and annotated Fig. 3, para [0026] describes wherein the conductive connection structure of the connection substrate CS comprising the through vias 112A is coupled to conductive features 106B of the second integrated circuit 106 electrically connecting it to the package substrate 300 through terminals 114 and package substrate bonding pads 300B).
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Regarding Claim 2, Islam teaches the semiconductor package of claim 1,
wherein the first integrated circuit device comprises a plurality of first connection pads provided on an upper surface of the first integrated circuit device (108C, Fig. 3, para [0037] describes wherein second bonding elements 108C provided on an upper surface of the first integrated circuit device 108 may be conductive pads),
the second integrated circuit device comprises a plurality of second connection pads provided on a lower surface of the second integrated circuit device (106C, Fig. 3, para [0037] describes wherein first bonding elements 108C provided on a lower surface of the second integrated circuit device 106 may be conductive pads), and
the plurality of first connection pads are directly and respectively bonded to the plurality of second connection pads (106C and 108C, Fig. 3, para [0037] describes wherein the first connection pads 108C and the second connection pads 106C may be bonded to one another).
Regarding Claim 5, Islam teaches the semiconductor package of claim 1,
wherein the connection substrate comprises an insulating base layer (CS and 110, annotated Fig. 3, para [0024] describes wherein the connection substrate CS comprises an insulating material layer 110),
wherein the insulating base layer comprises a mold-based base layer (110, Fig. 3, para [0024] describes wherein the insulating base layer 110 may further include polymers such as epoxy resins constituting a mold-based base layer),
wherein the first conductive connection structure of the connection substrate penetrates the mold-based base layer and comprises a plurality of through electrodes (112A, Fig. 1J and annotated Fig. 3, para [0026] describes wherein the first conductive connection structure of the connection substrate CS comprises a plurality of through vias 112A penetrating the insulating base layer 110 comprising the mold-based base layer), and
wherein the plurality of through electrodes comprises a plurality of mold through electrodes (112A, Fig. 3, para [0026] describes wherein the plurality of through electrodes 112A penetrate through the insulating layer 110 comprising the mold-based base layer therefore the plurality of through electrodes 112A comprise a plurality of mold through electrodes), the plurality of mold through electrodes configured to electrically connect the second integrated circuit device and the package substrate (112A, Fig. 3, para [0026] describes wherein the plurality of mold through electrodes 112A electrically connect the second integrated circuit device 106 and the package substrate 300).
Regarding Claim 11, Islam teaches the semiconductor package of claim 1,
wherein the connection substrate comprises an insulating base layer (CS and 110, annotated Fig. 3, para [0024] describes an insulating material 110 of the connection substrate CS), and
the first conductive connection structure of the connection substrate comprises a plurality of redistribution patterns in the insulating base layer (112A, Fig. 1J and annotated Fig. 3, para [0026] describes through vias 112A of the first conductive connection structure of the connection substrate CS wherein the metal through vias 112A are a plurality of redistribution patterns in the insulating base layer 110).
Regarding Claim 13, Islam teaches the semiconductor package of claim 1,
wherein the first integrated circuit device comprises a photonic integrated circuit device (108, Fig. 3, para [0020] describes wherein the first integrated circuit 108 may be a photonic die), and the second integrated circuit device comprises an electronic integrated circuit device (106, Fig. 3, para [0018] describes wherein the second integrated circuit device 106 may be an electronic die including electronic devices).
Regarding Claim 15, Islam teaches a semiconductor package comprising:
a package substrate (300, Fig. 3, para [0031] describes a package component 300 which may be a package substrate);
a connection substrate mounted on the package substrate (CS, Fig. 1J and annotated Fig. 3 depicts a connection substrate CS mounted on the package substrate 300 wherein para [0024] describes the connection substrate CS comprises an insulating material 110 and through vias 112A), the connection substrate including a mold-based base layer (110, annotated Fig. 3, para [0024] describes wherein the insulating base layer 110 of the connection substrate CS may further include polymers such as epoxy resins constituting a mold-based base layer) and a plurality of mold through electrodes penetrating the mold-based base layer (112A, Fig. 1J and annotated Fig. 3, para [0026] describes wherein the connection substrate CS comprises a plurality of through vias 112A penetrating the mold-based base layer 110 resulting in mold through electrodes 112A);
a photonic integrated circuit device mounted on the package substrate and configured to transceive optical signals via an optical fiber (108 and 304, Fig. 3, para [0021] describes a photonic integrated circuit device 108 including optical devices mounted on the package substrate 300 and para [0034] describes an optical fiber 304 attached to a side surface of the photonic integrated circuit device 108 for sending and/or receiving light signals to the photonic integrated circuit device 108); and
an electronic integrated circuit device mounted on the photonic integrated circuit device and the connection substrate (106, annotated Fig. 3, para [0018] describes an electronic die 106 including electronic devices disposed on the connection substrate CS and the first integrated circuit device 108) and configured to process a signal provided by the photonic integrated circuit device (106 and 108, Fig. 3, para [0021] describes wherein the electronic integrated circuit device 106 may process signals from the photonic integrated circuit device 108),
wherein the electronic integrated circuit device is directly connected to the photonic integrated circuit device and the connection substrate (106B and 106C, annotated Fig. 3, para [0037] describes wherein the electronic integrated circuit device 106 is directly connected to the photonic integrated circuit device 108 through conductive pads 106C and directly connected to the connection substrate CS through conductive pads 106B), and
the electronic integrated circuit device is electrically connected to the package substrate via the plurality of mold through electrodes (106, 106B, 112A, 300B and CS, Fig. 1J and annotated Fig. 3, para [0026] describes wherein the mold through electrodes 112A is coupled to conductive pads 106B of the electronic integrated circuit device 106 electrically connecting it to the package substrate 300 through terminals 114 and package substrate bonding pads 300B).
Claim 20-21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Omkar G. Karhade et al. (US 2023/0411369 A1; hereinafter “Karhade”).
Regarding Claim 20, Karhade teaches a semiconductor package comprising:
a package substrate (302, Fig. 3B, para [0041] describes a substrate 302 of package 300);
a connection substrate mounted on the package substrate (310, Fig. 3B, para [0041] describes a cavity bride 310 mounted on the package substrate 302);
a first integrated circuit device mounted on the package substrate (314, Fig. 3B, para [0042] describes a photonic integrated circuit 314 mounted on the package substrate 302);
a second integrated circuit device disposed on the connection substrate and the first integrated circuit device (316, Fig. 3B, para [0041] describes an electronic integrated circuit 316 disposed on the connection substrate 310 and first integrated circuit device 314), wherein the second integrated circuit device is directly connected to the first integrated circuit device (316 and 314, Fig. 3B, para [0045] describes wherein the second integrated circuit 316 includes conductive contacts 307 which are directly connected to the first integrated circuit 314) and electrically connected to the package substrate via the connection substrate (316, 312 and 302, Fig. 3B, para [0041] describes through-hole vias 312 electrically connecting the second integrated circuit 316 to the package substrate 302); and
a third integrated circuit device mounted on the connection substrate (318, Fig. 3B, para [0041] describes a packaged computing component 318 mounted on the connection substrate 310) and electrically connected to the second integrated circuit device via the connection substrate (318, 311 and 316, Fig. 3B, para [0041] describes conductive traces 311 of the connection substrate 310 electrically connecting the third integrated circuit device 318 and second integrated circuit device 316),
wherein one of the first integrated circuit device and the second integrated circuit device comprises a photonic integrated circuit device to which an optical fiber is attached (314 and 315, Fig. 3B, para [0043] describes wherein the first integrated circuit device 314 is a photonic integrated circuit with an optical fiber array 315 attached), and the other of the first integrated circuit device and the second integrated circuit device comprises an electronic integrated circuit device (316, Fig. 3B, para [0041] describes wherein the second integrated circuit device 316 is an electronic integrated circuit device).
Regarding Claim 21, Karhade teaches semiconductor package of claim 20,
wherein the connection substrate further comprises:
a silicon-based base layer (110 and 310, Fig. 1 and Fig. 3B, para [0030] describes wherein a cavity bridge 110 may be a silicon cavity bridge wherein cavity bridge 310 from Fig. 3B may be comprises of a same silicon cavity bridge material);
a plurality of through electrodes penetrating the silicon-based base layer (312, Fig. 3B, para [0041] describes through-hole vias 312 penetrating the silicon-based cavity bridge 310 base layer); and
a redistribution structure disposed on the silicon-based base layer (311, Fig. 3B, para [0041] describes conductive traces 311 of a redistribution structure disposed on and in the silicon-based connecting substrate 310 base layer), and the redistribution structure comprising a plurality of redistribution patterns electrically connected to the plurality of through electrodes (311, Fig. 3B, para [0041] describes wherein the redistribution structure comprising a plurality of redistribution patterns 311 are electrically connected to the plurality of through electrodes 312 through the second integrated circuit device 316 and third integrated circuit device 318),
wherein the second integrated circuit device is electrically connected to the package substrate via at least one of the plurality of through electrodes (316, 312 and 302, Fig. 3B, para [0041] describes the through-hole vias 312 electrically connecting the second integrated circuit 316 to the package substrate 302), and
wherein the second integrated circuit device is electrically connected to the third integrated circuit device via the plurality of redistribution patterns (318, 311 and 316, Fig. 3B, para [0041] describes wherein the plurality of redistribution patterns 311 of the connection substrate 310 electrically connecting the third integrated circuit device 318 and second integrated circuit device 316).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Rabiul Islam et al. (2021/0225824 A1; hereinafter “Islam”) in view of Yu-Kuang Liao et al. (US 10,333,623 B1; hereinafter “Liao”).
Regarding Claim 3, Islam discloses all the limitations of claim 2.
Islam fails to explicitly disclose the semiconductor package of claim 2, wherein the first integrated circuit device comprises a first pad insulating layer surrounding the plurality of first connection pads, wherein the second integrated circuit device comprises a second pad insulating layer surrounding the plurality of second connection pads, and wherein the first pad insulating layer is directly bonded to the second pad insulating layer.
However, Liao teaches a similar semiconductor package, wherein the first integrated circuit device (100, Fig. 1B, column 2, lines 37-40 describe a first photonic integrated circuit component 100) comprises a first pad insulating layer (130, Fig. 1B, column 3, lines 1-8 describe a first dielectric layer 130 of the first integrated circuit device 100) surrounding the plurality of first connection pads (130 and 140, Fig. 1B, column 3, lines 4-7 describe wherein the first dielectric layer 130 surround a plurality of first conductors 140 comprising connection pads),
wherein the second integrated circuit device (200, Fig. 1B, column 3, lines 45-58 describe a second electric integrated circuit component 200) comprises a second pad insulating layer (230, Fig. 1B, column 3, lines 49-53 describe a second dielectric layer 230 of the second integrated circuit device 200) surrounding the plurality of second connection pads (230 and 240, Fig. 1B, column 3, lines 52-55 describe wherein the second dielectric layer 230 surround a plurality of second conductors 240 comprising connection pads), and
wherein the first pad insulating layer is directly bonded to the second pad insulating layer (130 and 230, Fig. 1B, column 5, lines 20-27 describe bonding the first pad insulating layer 130 to the second pad insulating layer 230).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Islam with Liao to further disclose a semiconductor package wherein a first integrated circuit device comprises a first pad insulating layer surrounding a plurality of first connection pads, wherein a second integrated circuit device comprises a second pad insulating layer surrounding a plurality of second connection pads, and wherein the first pad insulating layer is directly bonded to the second pad insulating layer in order to provide the advantage of providing a surface which may be pre-bonded to increase the bonding strength between two integrated circuit devices (Liao, column 5, lines 1-4) and to provide the well-known advantage of surrounding conductive pads with dielectric material to prevent current leakage to neighboring device components when bonding two integrated circuit devices together.
Regarding Claim 4, the combination of Islam and Liao teaches the semiconductor package of claim 3, wherein each of the first pad insulating layer (130, Fig. 1B, column 3, lines 10-11 describes wherein the first pad insulating layer 130 may comprise silicon oxide) and the second pad insulating layer comprises silicon oxide (230, Fig. 1B, column 3, lines 59-61 describes wherein the second pad insulating layer 230 may comprise silicon oxide).
Claims 6, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Rabiul Islam et al. (2021/0225824 A1; hereinafter “Islam”) in view of Hyuekjae Lee et al. (US 2021/0358875 A1; hereinafter “Lee”).
Regarding Claim 6, Islam discloses all the limitations of claim 5.
Islam teaches the semiconductor package of claim 5,
wherein the first integrated circuit device (108, Fig. 3) comprises a plurality of first connection pads provided on an upper surface of the first integrated circuit device (108c, Fig. 3, para [0037] describes conductive pads provided on an upper surface of the first integrated circuit device 108),
wherein the second integrated circuit device (106, Fig. 3) comprises a plurality of second connection pads provided on a lower surface of the second integrated circuit device (106c, Fig. 3, para [0037] describes conductive pads provided on a lower surface of the second integrated circuit device 106),
wherein some second connection pads among the plurality of second connection pads are directly and respectively bonded to the plurality of first connection pads (108c and 106c, Fig. 3, para [0037] describes wherein at least some of the second connection pads 106c of the plurality of second connection pads 106c is directly and respectively bonded to the plurality of first connection pads 108c),
Islam fails to explicitly disclose a first pad insulating layer surrounding the plurality of first connection pads, a second pad insulating layer surrounding the plurality of second connection pads, wherein the connection substrate comprises a plurality of third connection pads respectively connected to the plurality of mold through electrodes and a third pad insulating layer surrounding the plurality of third connection pads, wherein the other second connection pads among the plurality of second connection pads are directly and respectively bonded to the plurality of third connection pads, and wherein each of the first pad insulating layer and the third pad insulating layer is directly bonded to the second pad insulating layer.
However, Lee teaches a similar semiconductor package wherein the first integrated circuit device (140, Fig. 6, para [0036] describes a first semiconductor chip 140) comprises a first pad insulating layer (BO1, Fig. 6, para [0036] describes a first bond insulating layer BO1) surrounding the plurality of first connection pads (BO1 and BP1, Fig. 6, para [0036] describes wherein the first pad insulating layer BO1 is surrounding a plurality of first connection pads BP1),
wherein the second integrated circuit device (150, Fig. 6, para [0036] describes a second semiconductor chip 150) comprises a second pad insulating layer (B02, Fig. 6, para [0036] describes a second bond insulating layer BO1) surrounding the plurality of second connection pads (B02, BP2 and BP4, Fig. 6, para [0036] describes wherein the second pad insulating layer B02 is surrounding a plurality of second connection pads BP2 and BP4),
wherein the connection substrate (CS2, annotated Fig. 6 depicts a connection substrate CS2 connecting a package substrate 130 to the second semiconductor chip 150) comprises a plurality of third connection pads respectively connected to the plurality of mold through electrodes (BP3 and CP, annotated Fig. 6, para [0048] describes connection members CP in the form of metal through vias connected to a plurality of third connection pads BP3 on the connection members CP as describes in para [0037]) and a third pad insulating layer surrounding the plurality of third connection pads (BO1 and BP3, annotated Fig. 6 depicts wherein the connection substrate CS2 comprises a portion of pad insulating layer BO1 surrounding the third connection pads BP3 wherein the portion of pad insulating layer BO1 surrounding the third connection pads BP3 of the connection substrate CS2 constitutes a third pad insulating layer BO1 in CS2),
wherein the other second connection pads among the plurality of second connection pads are directly and respectively bonded to the plurality of third connection pads (BP4 and BP3, Fig. 6, para [0037] describes wherein the second connection pads that are not connected to the first bond pads, BP4, are directly contacting the plurality of third connection pads BP3 wherein para [0085] further describes bonding the directly contacting connection pads BP3 and BP4), and
wherein each of the first pad insulating layer and the third pad insulating layer is directly bonded to the second pad insulating layer (BO1, B02 and CS2, annotated Fig. 6, para [0085] describes wherein the first pad insulating layer BO1 and third pad insulating layer BO1 located in connection substrate region CS2, is directly bonded to the second pad insulating layer B02).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Islam with Lee to further disclose a semiconductor package comprising a first pad insulating layer surrounding the plurality of first connection pads, a second pad insulating layer surrounding the plurality of second connection pads, wherein the connection substrate comprises a plurality of third connection pads respectively connected to the plurality of mold through electrodes and a third pad insulating layer surrounding the plurality of third connection pads, wherein the other second connection pads among the plurality of second connection pads are directly and respectively bonded to the plurality of third connection pads, and wherein each of the first pad insulating layer and the third pad insulating layer is directly bonded to the second pad insulating layer in order to provide the advantage of enabling bond pad features between devices and between devise and connection structures without bumps which may improve thermal conductivity and allow for decreased size in connection pads improving integration and package speed (Lee, para [0050]) and to further provide the well-known advantage of surrounding conductive pads with dielectric material to prevent current leakage to neighboring device components when bonding two integrated circuit devices together.
Regarding Claim 16, Islam discloses all the limitations of claim 15.
Islam teaches the semiconductor package of claim 15,
wherein the photonic integrated circuit device (108, Fig. 3) comprises a plurality of first connection pads provided on an upper surface of the photonic integrated circuit device (108c, Fig. 3, para [0037] describes conductive pads provided on an upper surface of the first integrated circuit device 108),
wherein the electronic integrated circuit device (106, Fig. 3) comprises a plurality of second connection pads provided on a lower surface of the electronic integrated circuit device (106c, Fig. 3, para [0037] describes conductive pads provided on a lower surface of the second integrated circuit device 106),
wherein one or more second connection pads among the plurality of second connection pads are directly and respectively bonded to the plurality of first connection pads (108c and 106c, Fig. 3, para [0037] describes wherein at least some of the second connection pads 106c of the plurality of second connection pads 106c is directly and respectively bonded to the plurality of first connection pads 108c),
Islam fails to explicitly disclose a first pad insulating layer surrounding the plurality of first connection pads, a second pad insulating layer surrounding the plurality of second connection pads, wherein the connection substrate comprises a plurality of third connection pads connected to the plurality of mold through electrodes and a third pad insulating layer surrounding the plurality of third connection pads, wherein other second connection pads different from the one or more second connection pads among the plurality of second connection pads are directly and respectively bonded to the plurality of third connection pads, and wherein each of the first pad insulating layer and the third pad insulating layer is directly bonded to the second pad insulating layer.
However, Lee teaches a similar semiconductor package wherein the photonic integrated circuit device (140, Fig. 6, para [0036] describes a first semiconductor chip 140 wherein upon combining Islam with Lee the first semiconductor chip of Lee may be a photonic integrated circuit device chip) comprises a first pad insulating layer (BO1, Fig. 6, para [0036] describes a first bond insulating layer BO1) surrounding the plurality of first connection pads (BO1 and BP1, Fig. 6, para [0036] describes wherein the first pad insulating layer BO1 is surrounding a plurality of first connection pads BP1),
wherein the second integrated circuit device (150, Fig. 6, para [0036] describes a second semiconductor chip 150 wherein upon combining Lee Islam with Lee the second semiconductor chip of Lee may be an electronic integrated circuit device chip) comprises a second pad insulating layer (B02, Fig. 6, para [0036] describes a second bond insulating layer BO1) surrounding the plurality of second connection pads (B02, BP2 and BP4, Fig. 6, para [0036] describes wherein the second pad insulating layer B02 is surrounding a plurality of second connection pads BP2 and BP4),
wherein the connection substrate (CS2, annotated Fig. 6 depicts a connection substrate CS2 connecting a package substrate 130 to the second semiconductor chip 150) comprises a plurality of third connection pads connected to the plurality of mold through electrodes (BP3 and CP, annotated Fig. 6, para [0048] describes connection members CP in the form of metal through vias connected to a plurality of third connection pads BP3 on the connection members CP as describes in para [0037]) and a third pad insulating layer surrounding the plurality of third connection pads (BO1 and BP3, annotated Fig. 6 depicts wherein the connection substrate CS2 comprises a portion of pad insulating layer BO1 surrounding the third connection pads BP3 wherein the portion of pad insulating layer BO1 surrounding the third connection pads BP3 of the connection substrate CS2 constitutes a third pad insulating layer BO1 in CS2),
wherein other second connection pads different from the one or more second connection pads among the plurality of second connection pads are directly and respectively bonded to the plurality of third connection pads (BP4 and BP3, Fig. 6, para [0037] describes wherein the second connection pads that are not connected to the first bond pads, BP4, are directly contacting the plurality of third connection pads BP3 wherein para [0085] further describes bonding the directly contacting connection pads BP3 and BP4), and
wherein each of the first pad insulating layer and the third pad insulating layer is directly bonded to the second pad insulating layer (BO1, B02 and CS2, annotated Fig. 6, para [0085] describes wherein the first pad insulating layer BO1 and third pad insulating layer BO1 located in connection substrate region CS2, is directly bonded to the second pad insulating layer B02).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Islam with Lee to further disclose a semiconductor package comprising a first pad insulating layer surrounding the plurality of first connection pads, a second pad insulating layer surrounding the plurality of second connection pads, wherein the connection substrate comprises a plurality of third connection pads respectively connected to the plurality of mold through electrodes and a third pad insulating layer surrounding the plurality of third connection pads, wherein other second connection pads different from the one or more second connection pads among the plurality of second connection pads are directly and respectively bonded to the plurality of third connection pads, and wherein each of the first pad insulating layer and the third pad insulating layer is directly bonded to the second pad insulating layer in order to provide the advantage of enabling bond pad features between devices and between devise and connection structures without bumps which may improve thermal conductivity and allow for decreased size in connection pads improving integration and package speed (Lee, para [0050]) and to further provide the well-known advantage of surrounding conductive pads with dielectric material to prevent current leakage to neighboring device components when bonding two integrated circuit devices together.
Regarding Claim 17, the combination of Islam and Lee teaches the semiconductor package of claim 16, wherein each of the first pad insulating layer, the second pad insulating layer, and the third pad insulating layer comprises silicon oxide (BO1, BO2 and CS2, annotated Fig. 6, para [0051] describes wherein the first pad insulating layer BO1, the third pad insulating layer BO1 located in connection substrate region CS2 and the second pad insulating layer BO2 may comprise silicon oxide).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Rabiul Islam et al. (2021/0225824 A1; hereinafter “Islam”) in view of Mayank Mayukh et al. (US 2023/0367087 A1; hereinafter “Mayukh”).
Regarding Claim 14, Islam discloses all the limitations of claim 1.
Islam fails to explicitly disclose the semiconductor package of claim 1, wherein the first integrated circuit device comprises an electronic integrated circuit device, and the second integrated circuit device comprises a photonic integrated circuit device.
However, Mayukh teaches a similar semiconductor package,
wherein the first integrated circuit device comprises an electronic integrated circuit device (525, Fig. 5, para [0044] describes a semiconductor package 500 comprising a first integrated circuit mounted on a package substrate 505 wherein the first integrated circuit device 525 is an electronic integrated circuit device), and the second integrated circuit device comprises a photonic integrated circuit device (520, Fig. 5, para [0044] describes a second integrated circuit mounted on the first integrated circuit 525 and an interposer 510 wherein the second integrated circuit device 520 is a photonic integrated circuit device).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Islam with Mayukh to further disclose a semiconductor package wherein a first integrated circuit device comprises an electronic integrated circuit device, and a second integrated circuit device comprises a photonic integrated circuit device in order to provide the well-known advantage of enabling a photonic integrated circuit to be disposed in an area of a semiconductor package where it may have at least a side surface exposed in order to enable an optical fiber to be connected and for an electronic integrated circuit to be disposed in a connection substrate which may further provide the well-known advantage of increasing throughput for the electronic integrated circuit and enabling the EIC to be in electrical communication with multiple different integrated circuits in the semiconductor package.
Conclusion
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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