Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/29/2024 has been considered by the examiner.
Oath/Declaration
Oath/Declaration as file 05/29/2024 is noted by the Examiner.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 discloses the limitation “…a first voltage drop VD1 at a test metalization of the integrated circuit while driving the first current I1…” The underlined limitation in question appears to refer to the “first test current” disclosed earlier in Claim 1. If this is the case, then please make the proper correction.
Claim 1 discloses the limitation “…calculating an impedance Z of the driver based on the first voltage difference VD1 and the second voltage difference VD2 …”. Earlier in Claim 1, “VD1” and “VD2” are used to identify “first voltage drop” and “second voltage drop” respectively; so to avoid confusion, please make the proper corrections.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 discloses the limitation “…a second test current I2 different from the first test current I1 from the first contact pad through a driver to the ground metallization;…” in lines 7-8 of Claim 1. It is not clear if the underlined limitation in question refers to the same “ground metallization of the integrated circuit” disclosed earlier in Claim 1 or if it refers to a different “ground metallization”. If this is the case, then please change the underlined limitation to “the ground metallization of the integrated circuit”.
Claim 1 discloses the limitation “…a second voltage drop VD2 at the test metalization while driving the second test current I2; and…” in lines 9-10 of Claim 1. It is not clear if the underlined limitation in question refers to the same “test metalization of the integrated circuit” disclosed earlier in Claim 1 or if it refers to a different “test metalization”. If this is the case, then please change the underlined limitation to “the test metaization of the integrated circuit”.
Claim 1 discloses the limitation “…calculating an impedance Z of the driver based on the first voltage difference VD1 and…” in lines 11-12 of Claim 1. It is not clear if the underlined limitation refers to the “driver of the integrated circuit” or the “driver to the ground metallization”; both of which have been disclosed earlier in Claim 1; or if it refers to a different “driver”. Please make the proper corrections.
Claim 1 recites the limitation "…calculating an impedance Z of the driver based on the first voltage difference VD1 and the second voltage difference VD2." in lines 11 and 12 or Claim 1. There is insufficient antecedent basis for this limitation in the claim. There is no prior disclosure of a “first voltage difference” nor a “second voltage difference” prior to this disclosure.
Claim 4 discloses the limitation “…opening a second switch of the integrated circuit coupled between the test metalization and the ground metallization;…” in lines 5-6 of Claim 1. It is not clear if the underlined limitation in question refers to the same “ground metallization of the integrated circuit” disclosed earlier in Claim 1 or if it refers to a different “ground metallization”. If this is the case, then please change the underlined limitation to “the ground metallization of the integrated circuit”.
Claim 4 discloses the limitation “…closing a first switch of the integrated circuit coupled between the test metalization and the first contact pad; opening a second switch of the integrated circuit coupled between the test metalization and the ground metallization; measuring a first test voltage at the test metalization while the first switch is closed and the second switch is open; opening the first switch; closing the second switch; and measuring a second test voltage at the test metalization while the first switch is open and the second switch is closed…” in lines 3-12 of Claim 4. It is not clear if the underlined limitation in question refers to the same “test metalization of the integrated circuit” disclosed earlier in Claim 1 or if it refers to a different “test metalization”. If this is the case, then please change the underlined limitation to “the test metalization of the integrated circuit”.
Claim 4 discloses the limitation “…measuring a first test voltage at the test metalization while the first switch is closed and the second switch is open; opening the first switch; closing the second switch; and measuring a second test voltage at the test metalization while the first switch is open and the second switch is closed…” in lines 7-12 of Claim 4. It is not clear if the underlined limitations in question refer to the same “first switch of the integrated circuit” and “second switch of the integrated circuit” disclosed earlier in Claim 4 or if it refers to a different “first switch” and “second switch”. If this is the case, then please change the underlined limitations to “the first switch of the integrated circuit” and “the second switch of the integrated circuit”, respectively.
Claim 5 discloses the limitation “…closing the first switch; opening the second switch; measuring a third test voltage at the test metalization while the first switch is closed and the second switch is open; opening the first switch; closing the second switch; and measuring a fourth test voltage at the test metalization while the first switch is open and the second switch is closed…” in lines 3-12 of Claim 5. It is not clear if the underlined limitations in question refer to the same “first switch of the integrated circuit” and “second switch of the integrated circuit” disclosed earlier in Claim 4 or if it refers to a different “first switch” and “second switch”. If this is the case, then please change the underlined limitations to “the first switch of the integrated circuit” and “the second switch of the integrated circuit”, respectively.
Claim 5 discloses the limitation “…measuring a third test voltage at the test metalization while the first switch is closed and the second switch is open; opening the first switch; closing the second switch; and measuring a fourth test voltage at the test metalization while the first switch is open and the second switch is closed…” in lines 5-10 of Claim 5. It is not clear if the underlined limitation in question refers to the same “test metalization of the integrated circuit” disclosed earlier in Claim 1 or if it refers to a different “test metalization”. If this is the case, then please change the underlined limitation to “the test metalization of the integrated circuit”.
Claim 6 discloses the limitation “…stopping an impedance calibration process of the driver; if the impedance Z does not match the reference impedance: adjusting a resistor of the driver; and calculating the impedance Z of the driver a second time after adjusting the resistor…” in lines 3-8 of Claim 6. It is not clear if the underlined limitations refer to the “driver of the integrated circuit” or the “driver to the ground metallization”; both of which have been disclosed earlier in Claim 1; or if they refer to a different “driver”. Please make the proper corrections.
Claim 7 discloses the limitation “…plurality of resistance paths that can each be selectively coupled or decoupled from contributing to the impedance Z of the driver.” in lines 2-3 of Claim 1. It is not clear if the underlined limitation refers to the “driver of the integrated circuit” or the “driver to the ground metallization”; both of which have been disclosed earlier in Claim 1; or if it refers to a different “driver”. Please make the proper corrections.
Claim 8 discloses the limitation “…coupling or decoupling one or more of the resistance paths from contributing to the impedance Z of the driver.” in lines 2-3 of Claim 1. It is not clear if the underlined limitation refers to the “driver of the integrated circuit” or the “driver to the ground metallization”; both of which have been disclosed earlier in Claim 1; or if it refers to a different “driver”. Please make the proper corrections.
Claim 10 discloses the limitation “…the test metalization cannot be electrically accessed by circuits external to the integrated circuit…” in lines 1-2 of Claim 10. It is not clear if the underlined limitation in question refers to the same “test metalization of the integrated circuit” disclosed earlier in Claim 1 or if it refers to a different “test metalization”. If this is the case, then please change the underlined limitation to “the test metalization of the integrated circuit”.
Claim 11 recites the limitation "… a driver and configured to drive data from the integrated circuit via the first contact pad and the ground metalization and …" in lines 5-6 of Claim 1. There is insufficient antecedent basis for this limitation in the claim. There is no prior disclosure of a “ground metallization” before this disclosure.
Claim 17 discloses the limitation “…measuring a first test voltage at the test metalization while driving the first test current while the first switch is closed…” in lines 9-10 of Claim 17. It is not clear if the underlined limitation in question refers to the same “test metalization of the integrated circuit” disclosed earlier in Claim 17 or if it refers to a different “test metalization”. If this is the case, then please change the underlined limitation to “the test metaization of the integrated circuit”.
Claim 17 discloses the limitation “…measuring a first test voltage at the test metalization while driving the first test current while the first switch …” in lines 9-10 of Claim 17. It is not clear if the underlined limitation in question refers to the same “first switch of the integrated circuit” disclosed earlier in Claim 17 or if it refers to a different “first switch”. If this is the case, then please change the underlined limitations to “the first switch of the integrated circuit”.
Claim 19 discloses the limitation “…coupling the test metalization to the ground metallization by closing a second switch of the integrated circuit; and measuring a second test voltage at the test metalization while the first switch is open and the second switch is closed.” in lines 4-7 of Claim 19. It is not clear if the underlined limitation in question refers to the same “test metalization of the integrated circuit” disclosed earlier in Claim 17 or if it refers to a different “test metalization”. If this is the case, then please change the underlined limitation to “the test metaization of the integrated circuit”.
Claim 19 discloses the limitation “…coupling the test metalization to the ground metallization by closing a second switch of the integrated circuit;…” in lines 4-5 of Claim 1. It is not clear if the underlined limitation in question refers to the same “ground metallization of the integrated circuit” disclosed earlier in Claim 17 or if it refers to a different “ground metallization”. If this is the case, then please change the underlined limitation to “the ground metallization of the integrated circuit”.
Claim 19 discloses the limitation “…opening the first switch; coupling the test metalization to the ground metallization by closing a second switch of the integrated circuit; and measuring a second test voltage at the test metalization while the first switch is open and the second switch is closed.” in lines 3-8 of Claim 19. It is not clear if the underlined limitations in question refer to the same “first switch of the integrated circuit” and “second switch of the integrated circuit” disclosed earlier in Claims 17 and 19 or if it refers to a different “first switch” and “second switch”. If this is the case, then please change the underlined limitations to “the first switch of the integrated circuit” and “the second switch of the integrated circuit”, respectively.
Claim 20 discloses the limitation “…a second test current different than the first test current through the driver between the first contact pad and ground metallization …” in lines 2-3 of Claim 17. It is not clear if the underlined limitation in question refers to the same “ground metallization of the integrated circuit” disclosed earlier in Claim 17 or if it refers to a different “ground metallization”. If this is the case, then please change the underlined limitation to “the ground metallization of the integrated circuit”.
Claim 20 discloses the limitation “…measuring a third test voltage at the test metalization while the first switch is closed and the second switch is open; and measuring a fourth test voltage at the test metalization while the first switch is open and the second switch is closed…” in lines 5-8 of Claim 20. It is not clear if the underlined limitation in question refers to the same “ground metallization of the integrated circuit” disclosed earlier in Claim 17 or if it refers to a different “ground metallization”. If this is the case, then please change the underlined limitation to “the ground metallization of the integrated circuit”.
Claim 20 discloses the limitation “…measuring a third test voltage at the test metalization while the first switch is closed and the second switch is open; and measuring a fourth test voltage at the test metalization while the first switch is open and the second switch is closed” in lines 4-7 of Claim 20. It is not clear if the underlined limitations in question refer to the same “first switch of the integrated circuit” and “second switch of the integrated circuit” disclosed earlier in Claims 17 and 19 or if it refers to a different “first switch” and “second switch”. If this is the case, then please change the underlined limitations to “the first switch of the integrated circuit” and “the second switch of the integrated circuit”, respectively.
Claims 2-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph as they further limit Claim 1.
Claims 12-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph as they further limit Claim 11.
Claims 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph as they further limit Claim 17.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 9-15 and 17 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Chen US 2016/0036417 (Hereinafter Chen).
Regarding claim 1, Chen teaches a method (Figs. 1-6), comprising:
driving (Figs. 1-6; voltage mode driver, 100), with a test circuit (Figs. 1-6; calibration circuit; 200A, 200B, 620, 620’) external to an integrated circuit (Figs. 1-6; integrated circuit, 600), a first test current I1 (Figs. 1-6; [0032-0038]; variable current source, 230; plurality of current sources, Q0, Q1,…Qn)) from a first contact pad (Figs. 1-6; [0019-0035]) of the integrated circuit (Figs. 1-6; integrated circuit, 600) through a driver (Figs. 1-6; voltage mode driver, 100) of the integrated circuit (Figs. 1-6; integrated circuit, 600) to a ground metallization (Figs. 1-6; [0023-0025, 0035]; variable current source, 230) of the integrated circuit (Figs. 1-6; integrated circuit, 600);
measuring (Figs. 1-6; [0021-0035]; voltage measurement), with the test circuit (Figs. 1-6; calibration circuit; 200A, 200B, 620, 620’), a first voltage drop VD1 (Figs. 1-6; [0021-0035]) at a test metalization (Figs. 1-6; [0021-0035]) of the integrated circuit (Figs. 1-6; integrated circuit, 600) while driving the first current I1 (Figs. 1-6; [0032-0038]; variable current source, 230; plurality of current sources, Q0, Q1,…Qn));
driving, with the test circuit (Figs. 1-6; calibration circuit; 200A, 200B, 620, 620’), a second test current I2 (Figs. 1-6; [0032-0038]; variable current source, 230; plurality of current sources, Q0, Q1,…Qn)) different from the first test current I1 (Figs. 1-6; [0032-0038]; variable current source, 230; plurality of current sources, Q0, Q1,…Qn)) from the first contact pad (Figs. 1-6; [0032-0038]) through a driver (Figs. 1-6; voltage mode driver, 100) to the ground metallization (Figs. 1-6; [0023-0025, 0035]; variable current source, 230);
measuring (Figs. 1-6; [0021-0035]; voltage measurement), with the test circuit (Figs. 1-6; calibration circuit; 200A, 200B, 620, 620’), a second voltage drop VD2 (Figs. 1-6; [0021-0035]) at the test metalization (Figs. 1-6; [0021-0035]) while driving the second test current I2 (Figs. 1-6; [0032-0038]; variable current source, 230; plurality of current sources, Q0, Q1,…Qn)); and
calculating an impedance Z (Figs. 1-6; [0021-0035]; impedance matching) of the driver (Figs. 1-6; voltage mode driver, 100) based on the first voltage difference VD1 (Figs. 1-6; [0021-0035]) and the second voltage difference VD2 (Figs. 1-6; [0021-0035]).
Regarding claim 2, Chen further teaches the method of claim 1, comprising calculating the impedance Z (Figs. 1-6; [0021-0035]; impedance matching) based on the first voltage drop VD1 (Figs. 1-6; [0021-0035]), the second voltage drop VD2 (Figs. 1-6; [0021-0035]), the first test current I1 (Figs. 1-6; [0021-0035]), and the second test current I2 (Figs. 1-6; [0021-0035]).
Regarding claim 3, Chen further teaches the method of claim 2, comprising calculating the impedance Z (Figs. 1-6; [0021-0035]; impedance matching) with the formula Z=(VD1−VD2)/(I1−I2) (Figs. 1-6; [0021-0035]).
Regarding claim 9, Chen further teaches the method of claim 1, comprising: calculating the impedance Z (Figs. 1-6; [0021-0035]; impedance matching) while the integrated circuit is incorporated in a wafer that includes a plurality of integrated circuit (Figs. 1-6; [0021-0035]; impedance matching); and dicing the integrated circuit form the wafer after calculating the impedance Z (Figs. 1-6; [0021-0035]; impedance matching).
Regarding claim 10, Chen further teaches the method of claim 9, wherein after dicing and packaging the integrated circuit (Figs. 1-6; integrated circuit, 600), the test metalization cannot be electrically accessed by circuits external to the integrated circuit (Figs. 1-6; integrated circuit, 600).
Regarding claim 11, Chen teaches an integrated circuit package (Figs. 1-6) comprising:
an integrated circuit die (Figs. 1-6; integrated circuit, 600) including:
a first contact pad (Figs. 1-6; [0019-0035]);
a second contact pad (Figs. 1-6; [0019-0035]);
a driver (Figs. 1-6; voltage mode driver, 100) and configured to drive data from the integrated circuit (Figs. 1-6; integrated circuit, 600) via the first contact pad (Figs. 1-6; [0019-0035]) and the ground metalization (Figs. 1-6; [0023-0025, 0035]; variable current source, 230) and including a resistive path (Figs. 1-6; [0019-0035]; resistance) coupled between the first contact pad (Figs. 1-6; [0019-0035]) and the ground metallization (Figs. 1-6; [0023-0025, 0035]; variable current source, 230);
a test metalization (Figs. 1-6; [0021-0035]);
a first switch (Figs. 1-6; [0021-0035]; MOS transistor, T1) coupled between the first contact pad and the test metalization (Figs. 1-6; [0021-0035]; MOS transistor, T1); and
a second switch (Figs. 1-6; [0021-0035]; MOS transistor, T2) coupled between the ground metallization and the test metalization (Figs. 1-6; [0021-0035]; MOS transistor, T2).
Regarding claim 12, Chen further teaches the integrated circuit package of claim 11, wherein the driver (Figs. 1-6; voltage mode driver, 100) includes a plurality of resistors (Figs. 1-6; [0019-0035]; resistors, resistance) that can be selectively coupled or decoupled from the resistive path (Figs. 1-6; [0019-0035]; resistors, resistance).
Regarding claim 13, Chen further teaches the integrated circuit package of claim 12 comprising a controller (Figs. 1-6; [0021-0035]; calibration controller, 260) configured to control the driver (Figs. 1-6; [0021-0035]; calibration controller, 260).
Regarding claim 14, Chen further teaches the integrated circuit package of claim 13, wherein the controller (Figs. 1-6; [0021-0035]; calibration controller, 260) is configured to store a calibration code that controls which resistors are coupled into the resistive path (Figs. 1-6; [0021-0035]; calibration controller, 260).
Regarding claim 15, Chen further teaches The integrated circuit package of claim 13, wherein the controller (Figs. 1-6; [0021-0035]; calibration controller, 260) and the driver (Figs. 1-6; voltage mode driver, 100) make up a physical layer of the integrated circuit (Figs. 1-6; [0021-0035]; calibration controller, 260).
Regarding claim 17, Chen teaches a method (Figs. 1-6), comprising:
applying a first driver (Figs. 1-6; voltage mode driver, 100) calibration code (Figs. 1-6; [0021-0035]; calibration controller, 260) from a test circuit (Figs. 1-6; calibration circuit; 200A, 200B, 620, 620’) to an integrated circuit (Figs. 1-6; integrated circuit, 600) external to the integrated circuit (Figs. 1-6; integrated circuit, 600); and
measuring, with the test circuit (Figs. 1-6; calibration circuit; 200A, 200B, 620, 620’), an impedance (Figs. 1-6; [0021-0035]; impedance matching) of a driver (Figs. 1-6; voltage mode driver, 100) of the integrated circuit (Figs. 1-6; integrated circuit, 600), by:
driving a first test current (Figs. 1-6; [0032-0038]; variable current source, 230; plurality of current sources, Q0, Q1,…Qn)) through the driver (Figs. 1-6; voltage mode driver, 100) between a first contact pad (Figs. 1-6; [0019-0035]) and a ground metallization (Figs. 1-6; [0023-0025, 0035]; variable current source, 230) of the integrated circuit (Figs. 1-6; integrated circuit, 600);
coupling a test metalization (Figs. 1-6; [0019-0035]) of the integrated circuit (Figs. 1-6; integrated circuit, 600) to the first contact pad (Figs. 1-6; [0019-0035]) by closing a first switch (Figs. 1-6; [0021-0035]; MOS transistor, T1) of the integrated circuit (Figs. 1-6; integrated circuit, 600) while driving the first test current (Figs. 1-6; [0032-0038]; variable current source, 230; plurality of current sources, Q0, Q1,…Qn)); and
measuring a first test voltage (Figs. 1-6; [0021-0035]; voltage measurement) at the test metalization (Figs. 1-6; [0019-0035]) while driving the first test current (Figs. 1-6; [0032-0038]; variable current source, 230; plurality of current sources, Q0, Q1,…Qn)) while the first switch is closed Figs. 1-6; [0021-0035]; MOS transistor, T1).
Allowable Subject Matter
Claims 4-8, 16 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims (As long as Applicant is able to overcome the Claim Objections as well as the Claim Rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph disclosed earlier in the Office Action).
The following is an examiner’s statement of reasons for allowance:
Regarding claim 4, the prior art does not teach or suggest, in combination with the rest of the limitations of claims 1, 2 and 3,
“…wherein measuring the first voltage value includes, while driving the first test current: closing a first switch of the integrated circuit coupled between the test metalization and the first contact pad; opening a second switch of the integrated circuit coupled between the test metalization and the ground metallization; measuring a first test voltage at the test metalization while the first switch is closed and the second switch is open; opening the first switch; closing the second switch; and measuring a second test voltage at the test metalization while the first switch is open and the second switch is closed, wherein the first voltage drop VD1 is a difference between the first test voltage and the second test voltage.”
Claim 5 is also allowed as it further limits objected claim 4.
Regarding claim 6, the prior art does not teach or suggest, in combination with the rest of the limitations of claim 1,
“…comprising, after calculating the impedance: comparing the impedance Z to a reference impedance; if the impedance Z matches the reference impedance, stopping an impedance calibration process of the driver; if the impedance Z does not match the reference impedance: adjusting a resistor of the driver; and calculating the impedance Z of the driver a second time after adjusting the resistor.”
Claims 7 and 8 are also allowed as they further limit objected claim 6.
Regarding claim 16, the prior art does not teach or suggest, in combination with the rest of the limitations of claim 11,
“…comprising: a molding compound encapsulating the integrated circuit die; and a plurality of electrical connectors, wherein the first contact pad and the second contact pad are electrically connected to respective electrical connectors, wherein the test metalization is not electrically connected to a respective electrical connector.”
Regarding claim 18, the prior art does not teach or suggest, in combination with the rest of the limitations of claim 17,
“…comprising: comparing the impedance to a reference impedance; if the impedance matches the reference impedance, stopping a calibration process of the driver; and if the impedance does not match the reference impedance, applying a second driver calibration code to the integrated circuit.”
Regarding claim 19, the prior art does not teach or suggest, in combination with the rest of the limitations of claim 17,
“…wherein measuring the impedance includes, while driving the first current: opening the first switch; coupling the test metalization to the ground metallization by closing a second switch of the integrated circuit; and measuring a second test voltage at the test metalization while the first switch is open and the second switch is closed.”
Claim 20 is also allowed as it further limits objected claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Clunn US 2009/0033339 - A vector impedance measurement system (100) includes a first radio frequency (RF) source (101) for providing energy to a test circuit.
Pelley US 2006/0170450 - An impedance matching between two integrated circuits is achieved using an impedance measuring circuit in the integrated circuit that contains an impedance-programmable output buffer (IPOB) that is to have its output impedance changed.
Lim et al. US 2016/0231757 - Representative implementations of devices and techniques provide detection of a voltage drift of an electrical component or system.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAUL J RIOS RUSSO whose telephone number is (571)270-3459. The examiner can normally be reached Monday-Friday: 10am-6pm, EST.
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/RAUL J RIOS RUSSO/Examiner, Art Unit 2858