DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 11 is objected to because of the following informalities:
Claim 11 is not clear because it recites the limitation “the storage units”, in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “the storage units” (as recited in line 3) is:
“the storage unit” (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2005/0280061 A1) (submitted by the Applicant from IDS filed on 05/29/2024).
As to claim 1, Lee discloses in Fig. 10 a three-dimensional (3D) memory device, comprising: a second semiconductor structure (comprising 101 & 101a, Fig. 10) comprising: an array of memory cells {“floating devices (FLD)” 101 includes an array of memory cells (“DRAM cells”), para. [0076]-[0078]} (Fig. 10, para. [0055]-[0056], [0076]-[0078]), each of the memory cells (“DRAM cells”, para. [0076]-[0078]) comprising a vertical transistor (comprising “SOI pillar” 124, “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) extending in a first direction (vertical direction) (Fig. 10, para. [0071], [0076]-[0078], [0086]), and a storage unit (“Capacitor”, Fig. 10) coupled to the vertical transistor (comprising “SOI pillar” 124, “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) (Fig. 10, para. [0076]-[0078]); a plurality of bit lines (BL/121, Figs. 3, 7 & 10) coupled to the memory cells (“DRAM cells” including “SOI pillars” 124, Fig. 10, para. [0076]-[0078]) each extending in a second direction (horizontal direction) perpendicular to the first direction (vertical direction) (Fig. 10, para. [0084]); and a plurality of word lines {WL/“control gate” 123, Figs. 3 & 10} coupled to the memory cells (“DRAM cells” including “SOI pillars” 124, Fig. 10, para. [0076]-[0078]) each extending in a third direction perpendicular to the first direction (vertical direction) and the second direction (horizontal direction) (Figs. 3, 7, 8 and 10, para. [0086]), wherein the vertical transistor (comprising “SOI pillar” 124, “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) comprises a semiconductor body (“SOI pillar” 124, para. [0051], [0076]-[0078]) extending in the first direction (vertical direction), and a gate structure (comprising “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) in contact with two opposite sides of the semiconductor body (“SOI pillar” 124, para. [0051], [0076]-[0078]) in the third direction and one side of the semiconductor body (“SOI pillar” 124, para. [0051], [0076]-[0078]) in the second direction (horizontal direction) (Figs. 8 & 10, para. [0071], [0075], [0086]); and a respective one of the bit lines (BL/121, Figs. 3, 7 & 10) and a respective storage unit (“Capacitor”, Fig. 10) are coupled to opposite ends of each one of the memory cells (“DRAM cells”, para. [0076]-[0078]) in the first direction (vertical direction) (see Fig. 10).
As to claim 2, as applied to claim 1 above, Lee discloses in Fig. 10 all claimed limitations including the limitation: wherein the vertical transistor (comprising “SOI pillar” 124, “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) is a tri-gate transistor in which the gate structure (comprising “control gate” 123 and “gate insulator layer” 183, Figs. 8) partially circumscribes the semiconductor body (124) in a plan view (Fig. 8).
As to claim 3, as applied to claim 1 above, Lee discloses in Fig. 10 all claimed limitations including the limitation: wherein the one side of the semiconductor body (“SOI pillar” 124, para. [0051], [0076]-[0078]) in the second direction (horizontal direction) is aligned with one edge of a respective one of the word lines (“WL”/123, Figs. 8 & 10) (Figs. 8, 10, para. [0086]).
As to claim 4, as applied to claim 1 above, Lee discloses in Fig. 10 all claimed limitations including the limitation: wherein the gate structure (comprising “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) comprises a gate electrode (“control gate” 123), and a gate dielectric (“gate insulator layer” 183) between the gate electrode (“control gate” 123) and the semiconductor body (“SOI pillar” 124, para. [0051], [0076]-[0078]) in the third direction (Figs. 8 and 10, para. [0071], [0075], [0086]).
As to claim 5, as applied to claims 1 and 4 above, Lee discloses in Fig. 10 all claimed limitations including the limitation: wherein the gate dielectrics (“gate insulator layer” 183) of two adjacent vertical transistors (comprising “SOI pillar” 124, “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) of the vertical transistors (comprising “SOI pillar” 124, “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) in the third direction are separate (Figs. 7, 8 & 10, para. [0071]).
As to claim 6, as applied to claim 1 above, Lee discloses in Fig. 10 all claimed limitations including the limitation: wherein the vertical transistor (comprising “SOI pillar” 124, “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) further comprises a source and a drain (“source/drain terminal”, para. [0074]) disposed at two ends of the semiconductor body (“SOI pillar” 124, para. [0051], [0076]-[0078]), respectively, in the first direction (vertical direction) (Figs. 8, 10, para. [0074]).
As to claim 7, as applied to claims 1 and 6 above, Lee discloses in Fig. 10 all claimed limitations including the limitation: wherein one of the source and the drain (“source/drain terminal”, para. [0074]) of the vertical transistor (comprising “SOI pillar” 124, “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) is coupled to the storage unit (“Capacitor”, Fig. 10) in a respective memory cell (“DRAM cells” including “SOI pillars” 124, Fig. 10, para. [0076]-[0078]) (Figs. 8 and 10).
As to claim 8, as applied to claims 1, 6 and 7 above, Lee discloses in Fig. 10 all claimed limitations including the limitation: wherein another one of the source and the drain (“source/drain terminal”, para. [0074]) of the vertical transistor (comprising “SOI pillar” 124, “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) is coupled to the respective bit line (BL/121, Figs. 3, 7 & 10) (see Figs. 8 & 10).
As to claim 9, as applied to claim 1 above, Lee discloses in Fig. 10 all claimed limitations including the memory device further comprising: a first semiconductor structure (comprising 103 & 151) comprising a peripheral circuit (“a logic circuit” 114) (Fig. 10, para. [0058]); and a bonding interface between the first semiconductor structure (comprising 103 & 151) and the second semiconductor structure (comprising 101 & 101a) in the first direction (vertical direction) (Fig. 10, para. [0055]-[0056]); wherein the array of memory cells (“DRAM cells” including “SOI pillars” 124, Fig. 10, para. [0076]-[0078]) is coupled to the peripheral circuit (“a logic circuit” 114) across the bonding interface (Fig. 10); and the bit lines (BL/121, Figs. 3, 7 & 10) are disposed between the vertical transistors (comprising “SOI pillar” 124, “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) and the bonding interface (Fig. 10).
As to claim 10, as applied to claim 1 above, Lee discloses in Fig. 10 all claimed limitations including the limitation: wherein two ends of the semiconductor body (“SOI pillar” 124, para. [0051], [0076]-[0078]) in the first direction (vertical direction) extend beyond the gate structure (comprising “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10), respectively (Fig. 10).
As to claim 11, as applied to claim 1 above, Lee discloses in Fig. 10 all claimed limitations including the limitation: wherein the second semiconductor structure (comprising 101 & 101a, Fig. 10) further comprises a pad-out interconnect layer (see “pad-out interconnect layer” as annotated in Fig. 10 below); and the storage unit (“Capacitor”, Fig. 10) are disposed between the vertical transistors (comprising “SOI pillar” 124, “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) and the pad-out interconnect layer (see “pad-out interconnect layer” as annotated in Fig. 10 below) (see annotated Fig. 10 below).
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As to claim 12, as applied to claim 1 above, Lee discloses in Fig. 10 all claimed limitations including the memory device further comprising: a first semiconductor structure (comprising 103 & 151) comprising a peripheral circuit (“a logic circuit” 114) (Fig. 10, para. [0058]); and a bonding interface (see “bonding interface” as annotated in Fig. 10 below) between the first semiconductor structure (comprising 103 & 151) and the second semiconductor structure (comprising 101 & 101a, Fig. 10) in the first direction (vertical direction) (see Fig. 10); wherein the array of memory cells (“DRAM cells” including “SOI pillars” 124, Fig. 10, para. [0076]-[0078]) is coupled to the peripheral circuit (“a logic circuit” 114) across the bonding interface (Fig. 10); the first semiconductor structure (comprising 103 & 151) further comprises a pad-out interconnect layer (see “pad-out interconnect layer” as annotated in Fig. 10 below); and the peripheral circuit (see “peripheral circuit” as annotated in Fig. 10 below)/(“a logic circuit” 114) is disposed between the bonding interface (see “bonding interface” as annotated in Fig. 10 below) and the pad-out interconnect layer (see “pad-out interconnect layer” as annotated in Fig. 10 below)/ (“a logic circuit” 114) (see annotated Fig. 10 below).
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As to claim 13, Lee discloses in Fig. 10 a memory system, comprising: a memory device (Fig. 10) configured to store data, and comprising: a second semiconductor structure (comprising 101 & 101a, Fig. 10) comprising: an array of memory cells (“DRAM cells” including “SOI pillars” 124, Fig. 10, para. [0076]-[0078]), each of the memory cells (“DRAM cells” including “SOI pillars” 124, Fig. 10) comprising a vertical transistor (comprising “SOI pillar” 124, “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) extending in a first direction (vertical direction) (Fig. 10, para. [0055]-[0056], [0071], [0076]-[0078], [0086]), and a storage unit (“Capacitor”, Fig. 10) coupled to the vertical transistor (comprising “SOI pillar” 124, “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) (Fig. 10, para. [0076]-[0078]); a plurality of bit lines (BL/121, Figs. 3, 7 & 10) coupled to the memory cells (“DRAM cells” including “SOI pillars” 124, Fig. 10) each extending in a second direction (horizontal direction) perpendicular to the first direction (vertical direction) (Fig. 10, para. [0084]); and a plurality of word lines {WL/“control gate” 123, Figs. 3 & 10} coupled to the memory cells (“DRAM cells” including “SOI pillars” 124, Fig. 10) each extending in a third direction perpendicular to the first direction (vertical direction) and the second direction (horizontal direction) (Figs. 3, 7, 8 and 10, para. [0086]), wherein the vertical transistor (comprising “SOI pillar” 124, “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) comprises a semiconductor body (“SOI pillar” 124, para. [0051], [0076]-[0078]) extending in the first direction (vertical direction) (Fig. 10, para. [0051], [0076]-[0078]), and a gate structure (comprising “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) in contact with two opposite sides of the semiconductor body (“SOI pillar” 124, para. [0051], [0076]-[0078]) in the third direction and one side of the semiconductor body (“SOI pillar” 124, para. [0051], [0076]-[0078]) in the second direction (horizontal direction) (Figs. 8 & 10, para. [0071], [0075], [0086]); and a respective one of the bit lines (BL/121, Figs. 3, 7 & 10) and a respective storage unit (“Capacitor”, Fig. 10) are coupled to opposite ends of each one of the memory cells (“DRAM cells” including “SOI pillars” 124, Fig. 10) in the first direction (vertical direction) (see Fig. 10); and a memory controller (“a logic circuit” 114) coupled to the memory device and configured to control the array of memory cells (“DRAM cells” including “SOI pillars” 124, Fig. 10, para. [0076]-[0078]) (Fig. 10, para. [0058]).
As to claim 14, Lee discloses in Fig. 10 a method for forming a three-dimensional (3D) memory device, comprising: forming a second semiconductor structure (comprising 101 & 101a, Fig. 10), comprising: forming an array of memory cells (“DRAM cells” including “SOI pillars” 124, Fig. 10, para. [0076]-[0078]), each of the memory cells (“DRAM cells” including “SOI pillars” 124, Fig. 10) comprising a vertical transistor (comprising “SOI pillar” 124, “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) extending in a first direction (vertical direction) (Fig. 10, para. [0055]-[0056], [0071], [0076]-[0078], [0086]), and a storage unit (“Capacitor”, Fig. 10) coupled to the vertical transistor (comprising “SOI pillar” 124, “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) (Fig. 10, para. [0076]-[0078]); forming a plurality of bit lines (BL/121, Figs. 3, 7 & 10) coupled to the memory cells (“DRAM cells” including “SOI pillars” 124, Fig. 10, para. [0076]-[0078]) each extending in a second direction (horizontal direction) perpendicular to the first direction (vertical direction) (Fig. 10, para. [0084]); and forming a plurality of word lines {WL/“control gate” 123, Figs. 3 & 10} coupled to the memory cells (“DRAM cells” including “SOI pillars” 124, Fig. 10) each extending in a third direction perpendicular to the first direction (vertical direction) and the second direction (horizontal direction) (Figs. 3, 7, 8 and 10, para. [0086]), wherein the vertical transistor (comprising “SOI pillar” 124, “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) comprises a semiconductor body (“SOI pillar” 124, para. [0051], [0076]-[0078]) extending in the first direction (vertical direction) (Fig. 10, para. [0051], [0076]-[0078]), and a gate structure (comprising “control gate” 123 and “gate insulator layer” 183, Figs. 8 & 10) in contact with two opposite sides of the semiconductor body (“SOI pillar” 124, para. [0051], [0076]-[0078]) in the third direction and one side of the semiconductor body (“SOI pillar” 124, para. [0051], [0076]-[0078]) in the second direction (horizontal direction) (Figs. 8 & 10, para. [0071], [0075], [0086]); and a respective one of the bit lines (BL/121, Figs. 3, 7 & 10) and a respective storage unit are coupled to opposite ends of each one of the memory cells (“DRAM cells” including “SOI pillars” 124, Fig. 10, para. [0076]-[0078]) in the first direction (vertical direction) (see Fig. 10).
As to claim 15, as applied to claim 14 above, Lee discloses in Fig. 10 all claimed limitations including the method further comprising: forming a first semiconductor structure (comprising 103 & 151) comprising a peripheral circuit (“a logic circuit” 114) (Fig. 10, para. [0058]); bonding the first semiconductor structure (comprising 103 & 151) and the second semiconductor structure (comprising 101 & 101a, Fig. 10) in a face-to-face manner, such that the array of memory cells (“DRAM cells” including “SOI pillars” 124, Fig. 10, para. [0076]-[0078]) is coupled to the peripheral circuit (114) across a bonding interface (see “bonding interface” as annotated in Fig. 10 below) (see annotated Fig. 10 below); and forming a pad-out interconnect layer (see “pad-out interconnect layer” as annotated in Fig. 10 below) on a backside of the first semiconductor structure or the second semiconductor structure (comprising 101 & 101a, Fig. 10) after the bonding.
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Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,033,967. Although the claims at issue are not identical, they are not patentably distinct from each other because all the claims recited in the present invention are recited within claims 1-20 of U.S. Patent No. 12,033,967.
Present Invention (Application No. 18/677,480)
Patent No. 12,033,967 (reference)
Claim 1: a three-dimensional (3D) memory device, comprising: a second semiconductor structure comprising: an array of memory cells, each of the memory cells comprising a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor; a plurality of bit lines coupled to the memory cells each extending in a second direction perpendicular to the first direction; and a plurality of word lines coupled to the memory cells each extending in a third direction perpendicular to the first direction and the second direction, wherein the vertical transistor comprises a semiconductor body extending in the first direction, and a gate structure in contact with two opposite sides of the semiconductor body in the third direction and one side of the semiconductor body in the second direction; and a respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction (see claim 1, lines 10-33, Patent No. 12,033,967).
Claim 1: a three-dimensional (3D) memory device, comprising: … a second semiconductor structure comprising: an array of memory cells, each of the memory cells comprising a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor; a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction; and a plurality of word lines coupled to the memory cells and each extending in a third direction perpendicular to the first direction and the second direction, wherein the vertical transistor comprises a semiconductor body extending in the first direction, and a gate structure in contact with two opposite sides of the semiconductor body in the third direction and one side of the semiconductor body in the second direction; and a respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction.
Claim 2: the 3D memory device of claim 1, wherein the vertical transistor is a tri-gate transistor in which the gate structure partially circumscribes the semiconductor body in a plan view (see claim 2, lines 38-41, Patent No. 12,033,967).
Claim 2: the 3D memory device of claim 1, wherein the vertical transistor is a tri-gate transistor in which the gate structure partially circumscribes the semiconductor body in a plan view.
Claim 3: the 3D memory device of claim 1, wherein the one side of the semiconductor body in the second direction is aligned with one edge of a respective one of the word lines (see claim 3, lines 42-44, Patent No. 12,033,967).
Claim 3: the 3D memory device of claim 1, wherein the one side of the semiconductor body in the second direction is aligned with one edge of a respective one of the word lines.
Claim 4: the 3D memory device of claim 1, wherein the gate structure comprises a gate electrode, and a gate dielectric between the gate electrode and the semiconductor body in the third direction (see claim 4, lines 45-48, Patent No. 12,033,967).
Claim 4: the 3D memory device of claim 1, wherein the gate structure comprises a gate electrode, and a gate dielectric between the gate electrode and the semiconductor body in the third direction.
Claim 5: the 3D memory device of claim 4, wherein the gate dielectrics of two adjacent vertical transistors of the vertical transistors in the third direction are separate (see claim 5, lines 49-51, Patent No. 12,033,967).
Claim 5: the 3D memory device of claim 4, wherein the gate dielectrics of two adjacent vertical transistors of the vertical transistors in the third direction are separate.
Claim 6: the 3D memory device of claim 1, wherein the vertical transistor further comprises a source and a drain disposed at two ends of the semiconductor body, respectively, in the first direction (see claim 6, lines 52-55, Patent No. 12,033,967).
Claim 6: the 3D memory device of claim 1, wherein the vertical transistor further comprises a source and a drain disposed at two ends of the semiconductor body, respectively, in the first direction.
Claim 7: the 3D memory device of claim 6, wherein one of the source and the drain of the vertical transistor is coupled to the storage unit in a respective memory cell (see claim 7, lines 56-58, Patent No. 12,033,967).
Claim 7: the 3D memory device of claim 6, wherein one of the source and the drain of the vertical transistor is coupled to the storage unit in a respective memory cell.
Claim 8: the 3D memory device of claim 7, wherein another one of the source and the drain of the vertical transistor is coupled to the respective bit line (see claim 8, lines 59-61, Patent No. 12,033,967).
Claim 8: the 3D memory device of claim 7, wherein another one of the source and the drain of the vertical transistor is coupled to the respective bit line.
Claim 9: the 3D memory device of claim 1, further comprising: a first semiconductor structure comprising a peripheral circuit; and a bonding interface between the first semiconductor structure and the second semiconductor structure in the first direction; wherein the array of memory cells is coupled to the peripheral circuit across the bonding interface; and the bit lines are disposed between the vertical transistors and the bonding interface (see claim 1, lines 1-3 & 34-37; and claim 9, lines 62-64, Patent No. 12,033,967).
Claims 1 and 9: “a three-dimensional (3D) memory device, comprising: a first semiconductor structure comprising a peripheral circuit…a bonding interface between the first semiconductor structure and the second semiconductor structure in the first direction, wherein the array of memory cells is coupled to the peripheral circuit across the bonding interface” and “wherein the bit lines are disposed between the vertical transistors and the bonding interface”.
Claim 10: the 3D memory device of claim 1, wherein two ends of the semiconductor body in the first direction extend beyond the gate structure, respectively (see claim 10, lines 65-67, Patent No. 12,033,967).
Claim 10: the 3D memory device of claim 1, wherein two ends of the semiconductor body in the first direction extend beyond the gate structure, respectively.
Claim 11: the 3D memory device of claim 1, wherein the second semiconductor structure further comprises a pad-out interconnect layer; and the storage units are disposed between the vertical transistors and the pad-out interconnect layer (see claim 11, lines 1-5, Patent No. 12,033,967).
Claim 11: the 3D memory device of claim 1, wherein the second semiconductor structure further comprises a pad-out interconnect layer; and the storage units are disposed between the vertical transistors and the pad-out interconnect layer.
Claim 12: the 3D memory device of claim 1, further comprising: a first semiconductor structure comprising a peripheral circuit; and a bonding interface between the first semiconductor structure and the second semiconductor structure in the first direction; wherein the array of memory cells is coupled to the peripheral circuit across the bonding interface; the first semiconductor structure further comprises a pad-out interconnect layer; and the peripheral circuit is disposed between the bonding interface and the pad-out interconnect layer (see claim 1, lines 1-3 & 34-37; and claim 12, lines 6-10, Patent No. 12,033,967).
Claims 1 and 12: “a three-dimensional (3D) memory device, comprising: a first semiconductor structure comprising a peripheral circuit…a bonding interface between the first semiconductor structure and the second semiconductor structure in the first direction, wherein the array of memory cells is coupled to the peripheral circuit across the bonding interface”; and “ wherein the first semiconductor structure further comprises a pad-out interconnect layer; and the peripheral circuit is disposed between the bonding interface and the pad-out interconnect layer”.
Claim 13: a memory system, comprising: a memory device configured to store data, and comprising: a second semiconductor structure comprising: an array of memory cells, each of the memory cells comprising a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor; a plurality of bit lines coupled to the memory cells each extending in a second direction perpendicular to the first direction; and a plurality of word lines coupled to the memory cells each extending in a third direction perpendicular to the first direction and the second direction, wherein the vertical transistor comprises a semiconductor body extending in the first direction, and a gate structure in contact with two opposite sides of the semiconductor body in the third direction and one side of the semiconductor body in the second direction; and a respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction; and a memory controller coupled to the memory device and configured to control the array of memory cells (see claim 13, Patent No. 12,033,967).
Claim 13: “a memory system, comprising: a memory device configured to store data, and comprising: …a second semiconductor structure comprising: an array of memory cells, each of the memory cells comprising a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor; a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction; and a plurality of word lines coupled to the memory cells and each extending in a third direction perpendicular to the first direction and the second direction, wherein the vertical transistor comprises a semiconductor body extending in the first direction, and a gate structure in contact with two opposite sides of the semiconductor body in the third direction and one side of the semiconductor body in the second direction; and a respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction… and a memory controller coupled to the memory device and configured to control the array of memory cells through the peripheral circuit, the bit lines, and the word lines”.
Claim 14: a method for forming a three-dimensional (3D) memory device, comprising: forming a second semiconductor structure, comprising: forming an array of memory cells, each of the memory cells comprising a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor; forming a plurality of bit lines coupled to the memory cells each extending in a second direction perpendicular to the first direction; and forming a plurality of word lines coupled to the memory cells each extending in a third direction perpendicular to the first direction and the second direction, wherein the vertical transistor comprises a semiconductor body extending in the first direction, and a gate structure in contact with two opposite sides of the semiconductor body in the third direction and one side of the semiconductor body in the second direction; and a respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction (see claim 14, Patent No. 12,033,967).
Claim 14: a method for forming a three-dimensional (3D) memory device, comprising: … forming a second semiconductor structure, comprising: forming an array of memory cells, each of the memory cells comprising a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor; forming a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction; and forming a plurality of word lines coupled to the memory cells and each extending in a third direction perpendicular to the first direction and the second direction, wherein the vertical transistor comprises a semiconductor body extending in the first direction, and a gate structure in contact with two opposite sides of the semiconductor body in the third direction and one side of the semiconductor body in the second direction; and a respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction…”.
Claim 15: the method of claim 14, further comprising: forming a first semiconductor structure comprising a peripheral circuit; bonding the first semiconductor structure and the second semiconductor structure in a face-to-face manner, such that the array of memory cells is coupled to the peripheral circuit across a bonding interface; and forming a pad-out interconnect layer on a backside of the first semiconductor structure or the second semiconductor structure after the bonding (see claim 14, col. 84, lines 46-49, and col. 85, lines 4-7; and claim 15, lines 8-11, Patent No. 12,033,967).
Claims 14 and 15: “a method for forming a three-dimensional (3D) memory device, comprising: forming a first semiconductor structure comprising a peripheral circuit…bonding the first semiconductor structure and the second semiconductor structure in a face-to-face manner, such that the array of memory cells is coupled to the peripheral circuit across a bonding interface”, and “forming a pad-out interconnect layer on a backside of the first semiconductor structure or the second semiconductor structure after the bonding”.
Claim 16: the method of claim 14, wherein forming the array of memory cells comprises: forming a stack of dielectric layers on a substrate; forming a semiconductor body extending from the substrate through the stack of dielectric layers; removing one of the stack of dielectric layers to expose part of the semiconductor body; forming a gate structure in contact with three sides of the exposed part of the semiconductor body; and forming a storage unit in contact with the semiconductor body (see claim 16, lines 11-21, Patent No. 12,033,967).
Claim 16: the method of claim 14, wherein forming the array of memory cells comprises: forming a stack of dielectric layers on a substrate; forming a semiconductor body extending from the substrate through the stack of dielectric layers; removing one of the stack of dielectric layers to expose part of the semiconductor body; forming a gate structure in contact with three sides of the exposed part of the semiconductor body; and forming a storage unit in contact with the semiconductor body.
Claim 17: the method of claim 16, wherein forming the semiconductor body comprises: etching an opening extending through the stack of dielectric layers to expose part of the substrate; and epitaxially growing the semiconductor body from the exposed part of the substrate in the opening (see claim 17, col. 85, lines 22-25 & col. 86, lines 1-2, Patent No. 12,033,967).
Claim 17: the method of claim 16, wherein forming the semiconductor body comprises: etching an opening extending through the stack of dielectric layers to expose part of the substrate; and epitaxially growing the semiconductor body from the exposed part of the substrate in the opening.
Claim 18: the method of claim 16, wherein removing one of the stack of dielectric layers comprises: etching a trench through at least part of the stack of dielectric layers to expose the one of the stack of dielectric layers, wherein the trench is etched aligned with one side of the semiconductor body to expose the semiconductor body from the side; and etching away the one of the stack of dielectric layers via the trench (see claim 18, lines 3-12, Patent No. 12,033,967)..
Claim 18: the method of claim 16, wherein removing one of the stack of dielectric layers comprises: etching a trench through at least part of the stack of dielectric layers to expose the one of the stack of dielectric layers, wherein the trench is etched aligned with one side of the semiconductor body to expose the semiconductor body from the side; and etching away the one of the stack of dielectric layers via the trench.
Claim 19: the method of claim 16, wherein forming the array of memory cells further comprise: doping a first end of the semiconductor body away from the substrate prior to forming the storage unit; removing the substrate to expose a second end of the semiconductor body opposite to the first end after forming the storage unit; and doping the exposed second end of the semiconductor body (see claim 19, lines 13-21, Patent No. 12,033,967).
Claim 19: the method of claim 16, wherein forming the array of memory cells further comprise: doping a first end of the semiconductor body away from the substrate prior to forming the storage unit; removing the substrate to expose a second end of the semiconductor body opposite to the first end after forming the storage unit; and doping the exposed second end of the semiconductor body.
Claim 20: the method of claim 19, forming the bit lines comprises forming a respective one of the bit lines on the doped second end of the semiconductor body (see claim 20, lines 22-24, Patent No. 12,033,967).
Claim 20: the method of claim 19, forming the bit lines comprises forming a respective one of the bit lines on the doped second end of the semiconductor body.
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 August 22, 2026
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