Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 18 is objected to because of the following informalities:
Regarding claim 18: It is not accurate to state “a negative configuration providing bias conditions” since “a negative configuration” is not a structure such as a circuit but rather is a set of voltage biases or bias conditions according to Applicant’s specification.
Examiner suggest amending the claim as follows:
The apparatus of claim 11, wherein a gate of a first transistor of the pre-decoder circuitry is configured to receive a first pre-decoded address signal, for providing a negative configuration selection signal , wherein the first pre-decoded address signal has a high voltage value or a low voltage value.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-6 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 2, 4 of U.S. Patent No. 12,002,537 (reference patent). Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reasons:
Regarding claim 1: Claim 1 of the reference patent teaches the subject matter of this claims.
Regarding claim 2: Claim 1 of the reference patent teaches the subject matter of this claims.
Regarding claim 3: Claim 2 of the reference patent teaches the subject matter of this claims.
Regarding claim 4: Claim 2 of the reference patent teaches the subject matter of this claims.
Regarding claim 5: Claim 4 of the reference patent teaches the subject matter of this claims.
Regarding claim 6: Claim 4 of the reference patent teaches the subject matter of this claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-10, 17, and 19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3: The claim refers to “a de-selection signal to the one of the plurality of memory cells for the positive configuration” but as Examiner already stated in the first Non-Final Rejection “one of ordinary skill in the art is not informed by Applicant's specification of how to differentiate between a negative configuration and a positive configuration in the context of providing a de-selection signal or in the context of the positive or negative configuration being referred to alone by itself with no mention of which signal, selection or de-selection, is being provided.” Therefore, Examiner's decision is that Applicant has failed to provide a definition in these cases. Accordingly, any reference in the claims to just a positive configuration or a negative configuration without the condition of providing a selection signal, for example specifying a de-selection signal instead, is deemed INDEFINITE. Claim 4 depends on claim 3.
Regarding claim 5: The claim refers to “a de-selection signal to the one of the plurality of memory cells for the negative configuration” but as Examiner already stated in the first Non-Final Rejection “one of ordinary skill in the art is not informed by Applicant's specification of how to differentiate between a negative configuration and a positive configuration in the context of providing a de-selection signal or in the context of the positive or negative configuration being referred to alone by itself with no mention of which signal, selection or de-selection, is being provided.” Therefore, Examiner's decision is that Applicant has failed to provide a definition in these cases. Accordingly, any reference in the claims to just a positive configuration or a negative configuration without the condition of providing a selection signal, for example specifying a de-selection signal instead, is deemed INDEFINITE. Claim 6 depends on claim 5.
Regarding claim 7: The claim claims “corresponding to [a] positive configuration providing bias conditions” and “corresponding to the positive configuration providing bias conditions”.
Examiner already stated in the first Non-Final Rejection “one of ordinary skill in the art is not informed by Applicant's specification of how to differentiate between a negative configuration and a positive configuration in the context of providing a de-selection signal or in the context of the positive or negative configuration being referred to alone by itself with no mention of which signal, selection or de-selection, is being provided.” Therefore, Examiner's decision is that Applicant has failed to provide a definition in these cases. Accordingly, any reference in the claims to just a positive configuration or a negative configuration without the condition of providing a selection signal, for example specifying a de-selection signal instead, is deemed INDEFINITE. It seems that, by stating “bias conditions”, Applicant is still attempting to include the bias conditions for de-selection signals but Applicant did not provide a definition to differential between a positive configuration and a negative configuration in regards to de-selection signals as Examiner explained in the previous office action, namely because one of the bias conditions for providing a de-selection signal is categorized as being a positive configuration but matches a bias condition for providing a de-selection signal categorized as being a negative configuration. Hence, Applicant is permitted to refer to a positive or a negative configuration only in regards to generating or providing a respective section signal.
Also, the claim states “providing bias conditions for positive configuration selection signals for a first gate of a first n-type transistor and a second gate of a second n-type transistor of the decoder circuitry”. In plain English, the claim is interpreted to mean “positive selection signals” are for (being provided to) a first gate and a second gate but such signals being received at the gates of the first and second n-type transistors were not referred to in the original disclosure as being selection signals but rather these signals, VG! and VG2, were referred to as voltages included in the bias conditions (see [0039] of the original disclosure).
Claims 8-10 depend on claim 7.
Regarding claims 8-10: Remove any reference to “negative configuration” or “positive configuration” that is mentioned alone without explicitly being in regards to bias for a single selection signal otherwise one of ordinary skill in the art does not know the metes and bounds of “a positive configuration” or “a negative configuration” as explained above.
One way to address the above is to amend the claims 7 as follows:
A method of operating memory, comprising:
providing a first pre-decoded address signal to a gate of a first transistor of pre-decoder circuitry for providing a positive configuration selection signal;
providing a second pre-decoded address signal to a gate of a second transistor of the pre- decoder circuitry for providing the positive configuration selection signal; and
providing bias conditions to a first gate of a first n-type transistor of decoder circuitry and a second gate of a second n-type transistor of the decoder circuitry for providing the positive configuration selection signal.
Regarding claim 17: The claim claims “to provide a selection signal corresponding to a negative configuration mode for the first gate and the second gate”. In plain English, the claim is interpreted to mean “a selection signal” is for (is provided to) the first gate and the second gate but such signals being received at the gates of the first and second n-type transistors were not referred to in the original disclosure as being selection signals but rather these signals, VG! and VG2, were referred to as voltages included in the bias conditions (see [0039] of the original disclosure).
Also, it is not accurate to state “a negative configuration providing bias conditions” since “a negative configuration” is not a structure such as a circuit but rather is a set of voltage biases or bias conditions.
Examiner suggest amending the claim as follows:
The apparatus of claim 11, wherein the pre-decoder circuitry is configured to provide bias conditions, for providing a negative configuration selection signal, to the first gate and the second gate in response to a first pre-decoded address signal having a low voltage value or a second pre-decoded address signal having the low voltage value.
Regarding claim 19: There are two instances of “a negative configuration” but it is not definite as to whether each is to refer to the negative configuration introduced in claim 18. In other words, it is not definite if the phrase “a negative configuration” in claim 18 is to provide the antecedent basis for each of the two instances.
Also, it is not accurate to state “a negative configuration providing bias conditions” since “a negative configuration” is not a structure such as a circuit but rather is a set of voltage biases or bias conditions according to Applicant’s specification.
Examiner suggest amending the claim as follows:
The apparatus of claim 18, wherein a gate of a second transistor of the pre-decoder circuitry is configured to receive a second pre-decoded address signal, for providing a negative configuration selection signal , wherein the second pre-decoded address signal has the high voltage value or the low voltage value.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 11, 14-16 is/are rejected under 35 U.S.C. 102(a)(1) as being antiicipated by Rana (US 2011/0299355).
Regarding claim 1: Rana (FIG. 6 and [0066-0068] disclose pre-decoder circuitry in ADDRESS DEOCER 112 of FIG. 1; FIGs. 3-5 teach bias conditions for two n-type transistors 202-2 and 202-3 in a word-line driver of FIG. 2 in different operations in accordance with TABLES 1-3, wherein word-lines are selected or de-selected using different bias conditions) teaches an apparatus, comprising:
a memory array (memory array 104 in FIG. 1; [0028]) including a plurality of memory cells (memory cells Cijk in FIG. 1; [0033]); and
pre-decoder circuitry (group decoder 114 in FIG. 1) configured to provide a bias condition for a first gate of a first n- type transistor and second gate of a second n-type transistor (each word-line driver 122-1 to 122-N in FIG. 1 is illustrated in FIG. 2, wherein the gate of transistor 202-2 is a first gate and the gate of transistor 202-3 is a second gate) to provide a selection signal (FIG. 4A; a selected signal on WLIJ having a VLOW=-8.5V during an erase operation, for example; see TABLE 2; [0059]) to one of the plurality of memory cells, wherein:
the bias condition comprises:
a positive voltage for the first gate (GPN=VHIGH in FIG. 5a; [0063-0064]; TABLE 3) and a negative voltage (GPH=VREF in FIG. 5; [0063-0064]; TABLE 3) for the second gate for a positive configuration for the memory cells; or
zero volts for the first gate (GPN=0 in FIG. 4a; [0060]; TABLE 2) and the negative voltage for the second gate (GPH=VLOW in FIG. 4a; [0060]; TABLE 2) for a negative configuration for the memory cells.
Regarding claim 2: Rana teaches the apparatus of claim 1, wherein the apparatus includes decoder circuitry (word-line driver system 120 in FIG. 1; [0035]) coupled to the memory array, wherein the decoder circuitry includes the first n-type transistor and the second n-type transistor (Again, each word-line driver 122-1 to 122-N in FIG. 1 is illustrated in FIG. 2, wherein the gate of transistor 202-2 is a first gate and the gate of transistor 202-3 is a second gate).
Regarding claim 3: In so far as definite, Rana teaches the apparatus of claim 1, wherein the pre-decoder circuitry is configured to provide an additional bias condition for the first gate and the second gate to provide a de-selection signal to the one of the plurality of memory cells for the positive configuration (TABLE 1 and any one of FIG. 3b-d or TABLE 2 and any one of FIG. 4b-d or TABLE3 and any one of FIG. 5b-d).
Regarding claim 4: In so far as definite, Rana (FIG. 4C or FIG. 4d or FIG. 5C or FG. 5d) teaches the apparatus of claim 3, wherein the additional bias condition comprises the negative voltage (VLOW or VREF) for the first gate and a different positive voltage (VDD) for the second gate.
Regarding claim 5: In so far as definite, Rana teaches the apparatus, wherein the pre-decoder circuitry is configured to provide an additional bias condition for the first gate and second gate to provide a de-selection signal to the one of the plurality of memory cells for the negative configuration (TABLE 2 and any one of FIG. 4b-d or TABLE 1 and any one of FIG. 3b-d).
Regarding claim 6: In so far as definite, Rana (FIG. 4C or FIG. 4d or FIG. 5C or FG. 5d) teaches the apparatus of claim 3, wherein the additional bias condition comprises the negative voltage (VLOW or VREF) for the first gate and a different positive voltage (VDD) for the second gate.
Regarding claim 11: Rana (FIG. 6 and [0066-0068] disclose pre-decoder circuitry in ADDRESS DEOCER 112 of FIG. 1; FIGs. 3-5 teach bias conditions for two n-type transistors 202-2 and 202-3 in a word-line driver of FIG. 2 in different operations in accordance with TABLES 1-3, wherein word-lines are selected or de-selected using different bias conditions) teaches an apparatus, comprising:
a memory array (memory array 104 in FIG. 1; [0028]) including a plurality of memory cells (memory cells Cijk in FIG. 1; [0033]);
decoder circuitry (word-line driver system 120 in FIG. 1; [0035]) coupled to the array of memory cells; and
pre-decoder circuitry (group decoder 114 in FIG. 1) configured to provide a bias condition for a first gate of a first n- type transistor of the decoder circuitry and a second gate of a second n-type transistor of the decoder circuitry (each word-line driver 122-1 to 122-N in FIG. 1 is illustrated in FIG. 2, wherein the gate of transistor 202-2 is a first gate and the gate of transistor 202-3 is a second gate) to provide a selection signal (FIG. 4A; a selected signal on WLIJ having a VLOW=-8.5V during an erase operation, for example; see TABLE 2; [0059]) to one of the plurality of memory cells, wherein;
the pre-decoder circuitry (FIG. 6 illustrates a group decoder element included in the group decoder 114 in FIG. 1) includes a decoding portion (602), a first level shift portion (604-1), and a second level shift portion (604-2);
the first n-type transistor (202-2) has a first source region (upper diffusion terminal of transistor 202-2) coupled to a first voltage source (SP in FIG. 2) and a shared drain region (lower diffusion terminal of transistor 202-2) coupled to the memory array; and
the second n-type transistor (202-3) has a second source region (lower diffusion terminal of transistor 202-3) coupled to a second voltage source (DECS) that is different than [from] the first voltage source, and the shared drain region coupled to the memory array (coupled via word-line WLIJ).
Regarding claim 14: Rana (FIG. 6; [0066-0068]) teaches the first level shift portion (POSITIVE LEVEL SHIFTER 604-1) is configured to increase a pre-decoded high voltage value (to Vpos) to provide a positive voltage (VSSUB) for the first gate.
Regarding claim 15: Rana (FIG. 6; [0066-0068]) teaches the second level shift portion (NEGATIVE LEVEL SHIFTER 604-2) is configured to decrease a pre-decoded high voltage value to provide a negative voltage for the second gate (VNEG).
Regarding claim 16: Rana teaches the apparatus of claim 11, wherein the bias condition provides a selection signal for a positive configuration for the array of memory cells (FIG. 4a, TABLE 2, GPH=VLOW and GPN=0 or FIG. 5a, TABLE 3, GPH= VREF, GPN= VHIGH).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7-10, 12-13, and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rana (US 2011/0299355) in view of Humphrey (US 2003/0042970).
Regarding claim 7: Rana (FIG. 6 and [0066-0068] disclose pre-decoder circuitry in ADDRESS DEOCER 112 of FIG. 1; FIGs. 3-5 teach bias conditions for two n-type transistors 202-2 and 202-3 in a word-line driver of FIG. 2 in different operations in accordance with TABLES 1-3, wherein word-lines are selected or de-selected using different bias conditions) teaches:
the apparatus of claim 11, wherein an input of an AND gate is configured to receive a first pre-decoded address signal (one of LX or LY or LZ), and another input of the AND gate is configured to receive a second pre-decoded address signal (another one of LX or LY or LZ; Inherently, each of these signals is a digital signal that is at times a low voltage and at other times high voltage such that a corresponding row address of the memory array in Rana is selected in a memory operation in accordance with TABLES 1-3); and
providing bias conditions for positive configurations selection signals for a first gate of a first n-type transistor of decoder circuitry and a second gate of a second n-type transistor of the decoder circuitry (each word-line driver 122-1 to 122-N in FIG. 1 is illustrated in FIG. 2, wherein the gate of transistor 202-2 is a first gate and the gate of transistor 202-3 is a second gate; bias conditions are seen in each of TABLES 1-3, wherein at least one word-line is selected).
In so far as definite Rana does not specifically teach:
providing the first pre-decoded address signal corresponding to positive configuration providing bias conditions to a gate of a first transistor of pre-decoder circuitry; and
providing the second pre-decoded address signal corresponding to the positive configuration providing bias conditions to a gate of a second transistor of the pre- decoder circuitry.
Humphrey (FIG. 7, FIG. 8; [0016]) teaches an AND gate comprising transistors, wherein inputs to the logical gate are received at gates of transistors.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of Humphrey into the device and/or method of Rana in a manner such that the AND gate 602 of Humphrey would comprise transistors connected like those of Humphrey (FIG. 7), wherein a gate of a first transistor would be configured to receive the first pre-decoded address signal having a pre-decoded high voltage value relative to a pre-decoded low voltage value; and a gate of a second transistor would be configured to receive the second pre-decoded address signal having the pre-decoded high voltage value. The motivation to do so would have been to use a CMOS transistor configuration to implement the AND logic gate. Such an implementation is typical in the art of CMOS circuit design.
Regarding claim 8: In so far as definite, Rana as modified above teaches the method of claim 7, wherein the first pre-decoded address signal corresponding to the positive configuration providing bias conditions has a high voltage value or a low voltage value and the second pre-decoded address signal corresponding to the positive configuration providing bias conditions has the high voltage value or the low voltage value (see above; each address signal is a digital signal that at times is low and other times is high, and each row of the memory array has an address, wherein each address bit may be low or high depending on the particular address; see any one of TABLES 1-3 and FIG. 6).
Regarding claim 9: In so far as definite, Rana as modified above teaches the method of claim 8, wherein the bias conditions for positive configuration selection signals are provided when the first pre-decoded address signal corresponding to the positive configuration providing bias conditions has the low voltage value or when the second pre-decoded address signal corresponding to the positive configuration providing bias conditions has the low voltage value (see any one of TABLES 1-3 and FIG. 6).
Regarding claim 10: In so far as definite, Rana as modified above teaches the method of claim 7, further comprising:
providing a first negative configuration pre-decoded address signal to the gate of the first transistor of the pre-decoder circuitry (see any one of TABLES 1-3 and FIG. 6); and
providing a second negative configuration pre-decoder address signal to the gate of the second transistor of the pre-decoder circuitry (see any one of TABLES 1-3 and FIG. 6).
Regarding claims 12-13: Rana (FIG. 6; [0066-0068]) teaches the apparatus of claim 11, wherein an input of an AND gate is configured to receive a first pre-decoded address signal (one of LX or LY or LZ) having a pre-decoded high voltage value relative to a pre-decoded low voltage value. Inherently, each is a digital signal that is at times a low voltage and at other times high voltage such that a row address of the memory array in Rana is selected in a memory operation.
Rana does not specifically teach:
a gate of a first transistor of the decoding portion is configured to receive a first pre-decoded address signal having a pre-decoded high voltage value relative to a pre-decoded low voltage value; and
(regarding claim 13) a gate of a second transistor of the decoding portion is configured to receive a second pre-decoded address signal having the pre- decoded high voltage value.
Humphrey (FIG. 7, FIG. 8; [0016]) teaches an AND gate comprising transistors, wherein inputs to the logical gate are received at gates of transistors.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of Humphrey into the device and/or method of Rana in a manner such that the AND gate 602 of Humphrey would comprise transistors connected like those of Humphrey (FIG. 7), wherein a gate of a first transistor would be configured to receive the first pre-decoded address signal having a pre-decoded high voltage value relative to a pre-decoded low voltage value; and (regarding claim 13) a gate of a second transistor would be configured to receive the second pre-decoded address signal having the pre-decoded high voltage value. The motivation to do so would have been to use a CMOS transistor configuration to implement the AND logic gate. Such an implementation is typical in the art of CMOS circuit design.
Regarding claim 17: Rana (FIG. 6; [0066-0068]) teaches the apparatus of claim 11, wherein an input of an AND gate is configured to receive a first pre-decoded address signal (one of LX or LY or LZ) and a second pre-decoded address signal (another one of LX or LY or LZ), wherein each may be high or low depending on the word line address being selected. Inherently, each is a digital signal that is at times a low voltage and at other times high voltage such that a row address of the memory array in Rana is selected in a memory operation.
In so far as definite, Rana does not specifically teach:
The apparatus of claim 11, wherein the pre-decoder circuitry is configured to provide a selection signal corresponding to a negative configuration mode for the first gate and the second gate when a first pre-decoded address signal corresponding to a negative configuration providing bias conditions for a selection signal has a low voltage value or when a second pre-decoded address signal corresponding to the negative configuration providing bias conditions for a selection signal has the low voltage value.
Humphrey (FIG. 7, FIG. 8; [0016]) teaches an AND gate comprising transistors, wherein inputs to the logical gate are received at gates of transistors.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of Humphrey into the device and/or method of Rana in a manner such that the AND gate 602 of Humphrey would comprise transistors connected like those of Humphrey (FIG. 7), wherein the pre-decoder circuitry would be configured to provide a selection signal corresponding to a negative configuration mode for the first gate and the second gate when a first pre-decoded address signal corresponding to a negative configuration providing bias conditions for a selection signal would have a low voltage value or when a second pre-decoded address signal corresponding to the negative configuration providing bias conditions for a selection signal would have the low voltage value.
The motivation to do so would have been to use a CMOS transistor configuration to implement the AND logic gate. Such an implementation is typical in the art of CMOS circuit design.
Regarding claims 18-19: Rana (FIG. 6; [0066-0068]) teaches the apparatus of claim 11, wherein an input of an AND gate is configured to receive a first pre-decoded address signal (one of LX or LY or LZ) and a second pre-decoded address signal (another one of LX or LY or LZ), wherein each may be high or low depending on the word line address being selected. Inherently, each is a digital signal that is at times a low voltage and at other times high voltage such that a row address of the memory array in Rana is selected in a memory operation.
Rana does not specifically teach:
The apparatus of claim 11, wherein
a gate of a first transistor of the pre-decoder circuitry is configured to receive a first pre-decoded address signal corresponding to a negative configuration providing bias conditions for a selection signal, wherein the first pre-decoded address signal corresponding to the negative configuration providing bias conditions for a selection signal has a high voltage value or a low voltage value; and
(regarding claim 19) a gate of a second transistor of the pre-decoder circuitry is configured to receive a second pre-decoded address signal corresponding to a negative configuration providing bias conditions for a selection signal, wherein the second pre-decoded address signal corresponding to a negative configuration providing bias conditions for a selection signal has the high voltage value or the low voltage value.
Humphrey (FIG. 7, FIG. 8; [0016]) teaches an AND gate comprising transistors, wherein inputs to the logical gate are received at gates of transistors.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of Humphrey into the device and/or method of Rana in a manner such that the AND gate 602 of Humphrey would comprise transistors connected like those of Humphrey (FIG. 7), wherein
a gate of a first transistor of the pre-decoder circuitry would be configured to receive a first pre-decoded address signal corresponding to a negative configuration providing bias conditions for a selection signal, wherein the first pre-decoded address signal corresponding to the negative configuration providing bias conditions for a selection signal would have a high voltage value or a low voltage value; and
(regarding claim 19) a gate of a second transistor of the pre-decoder circuitry would be configured to receive a second pre-decoded address signal corresponding to a negative configuration providing bias conditions for a selection signal, wherein the second pre-decoded address signal corresponding to a negative configuration providing bias conditions for a selection signal would have the high voltage value or the low voltage value.
The motivation to do so would have been to use a CMOS transistor configuration to implement the AND logic gate. Such an implementation is typical in the art of CMOS circuit design.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rana (US 2011/0299355) in view of Klass et al. (US 5,880,609).
Regarding claim 20: Rana teaches using an AND logic gate to provide the bias condition applied to the word-line driver that provides the selection signal.
Rana does not specifically teach a gate of a transistor of the decoding portion is configured to receive an enable signal having an enable high voltage value relative to an enable low voltage value to provide the bias condition that provides the selection signal.
Klass (FIG. 1, FIG. 2; lines 12-63 of column 1) teaches a conventional dynamic three-input AND logic gate, wherein the logic gate receives an enable signal (clock signal CK) having an enable high voltage value relative to an enable low voltage value to provide an output.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of Klass into the device and/or method of Rana in a manner such that the AND gate 602 would comprise a three-input dynamic AND gate like that taught by Klass, wherein a gate of an evaluation transistor of the decoding portion, like EV in FIG. 1 of Klass, would be configured to receive an enable signal such as a clock signal having an enable high voltage value relative to an enable low voltage value to enable the dynamic logic AND gate to evaluate and provide the bias condition that provides the selection signal. The motivation to do so would have been to use a dynamic logic gate to implement the three-input AND gate already disclosed by Rana since dynamic logic is known in general to allow the design oof faster circuits compared to conventional CMOS circuits as is disclosed by Klass.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection using the new reference of Rana does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827
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