DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 05/09/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings submitted on 05/29/2024. These drawings are review and accepted by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that recite functional language but are not interpreted under 35 U.S.C. 112(f). Such claim limitation(s) is/are:
Apparatus claims 8-14’s “circuitry for” that is “configured to” perform recited operations;
Apparatus claims 15-20’s “an erasing means for” that is “configured to” perform recited operations.
Because these claim limitation(s) are not being interpreted under 35 U.S.C. 112(f), they are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shukla et al (US 12,322,451 B2 hereinafter “Shukla”) in view of Zhao et al (US 11,557,358 B2 hereinafter “Zhao”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Shukla, for example in Figs. 1-5, discloses a method of performing an erase operation (see for example in Fig. 3 related in Figs. 1-2, 4-5) in a memory device (e.g., memory device; in Fig. 2 related in Figs. 1, 3-5), comprising the steps of: preparing a memory block (e.g., memory block 228; in Fig. 2 related in Figs. 1, 3-5) that includes an array of memory cells (e.g., MCs 222; in Fig. 2 related in Figs. 1, 35) that are arranged in a plurality of word lines (within memory array 202; in Fig. 2 related in Figs. 1, 3-5); applying at least one erase pulse to the memory block to erase the memory cells (e.g., erase pulse 182/482; in Figs. 1, 4 related in Figs. 2-3, 5) of a plurality of word lines of the plurality of word lines, the plurality of selected word lines including a plurality of memory cells (see for example in Fig. 3 related in Figs. 1-2, 4-5); suspending the at least one erase pulse for a suspend duration (see for example in Figs. 1, 4 related in Figs. 2-3, 5); and after the suspend duration and before applying a next erase pulse to the memory block (e.g., erase pulse 182/482; in Figs. 1, 4 related in Figs. 2-3, 5), performing an erase-verify operation on only a portion of the selected memory cells (e.g., 183; in Figs. 1, 4 related in Figs. 2-3, 5).
However, Shukla is silent with regard to a plurality of selected word lines of the plurality of word lines, the plurality of selected word lines including a plurality of selected memory cells.
In the same field of endeavor, Zhao, for example in Figs. 1-21, discloses a plurality of selected word lines of the plurality of word lines, the plurality of selected word lines including a plurality of selected memory cells (implied the step of 1300-1302; in Fig. 21 related in Figs. 1-20 and also see Abstract).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Shukla such as memory systems with flexible erase suspend-resume operations, and associated systems, devices, and methods (see for example in Figs. 1-5 of Shukla) by incorporating the teaching of Zhao such as memory apparatus and method of operation using adapted erase time compensation for segmented erase (see for example in Figs. 1-21 of Zhao), for the purpose of controlling the applying a word line erase voltage to selected ones of the word lines to encourage erasing of the memory cells coupled to the selected ones of the word lines in the segmented erase operation (Zhao, see Abstract).
Regarding claim 2, the above Shukla/Zhao, the combination discloses further including the steps of: during the step of performing the erase-verify operation on only the portion of the selected memory cells (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above), counting the number of memory cells that fail the erase-verify operation to establish a count (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above); and determining an erase pulse duration for the next erase pulse as a function of the count (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above).
Regarding claim 3, the above Shukla/Zhao, the combination discloses wherein the step of determining the erase pulse duration for the next erase pulse as a function of the count (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above) includes the steps of: comparing the count to a predetermined threshold (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above), setting the erase pulse duration at a first timeframe in response to the count being above the predetermined threshold (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above), and setting the erase pulse duration at a second timeframe in response to the count being below the predetermined threshold, and wherein the second timeframe is less than the first timeframe (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above).
Regarding claim 4, the above Shukla/Zhao, the combination discloses wherein the portion of selected memory cells includes the memory cells of a single string of a plurality of strings in the memory block (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above), and wherein in response to the single string of memory block passing the erase-verify operation, then the method further includes the step of verifying the remaining strings of the memory block (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above).
Regarding claim 5, the above Shukla/Zhao, the combination discloses wherein in response to any of the remaining strings of the memory block failing the erase-verify operation (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above), then the method further includes the step of setting the erase pulse duration at a third timeframe that is less than the second timeframe (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above).
Regarding claim 6, the above Shukla/Zhao, the combination discloses wherein the portion of selected memory cells includes the memory cells of a single string of a plurality of strings in the memory block (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above).
Regarding claim 7, the above Shukla/Zhao, the combination discloses wherein the plurality of selected word lines include all of the data word lines in the memory block (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above).
Regarding Independent Claim 8, Shukla, for example in Figs. 1-5, discloses a memory device (e.g., memory device 200; in Fig. 2 related in Figs. 1, 2-5) comprising: a memory block (e.g., blocks 228; in Fig. 2 related in Figs. 1, 2-5) with an array of memory cells that are arranged in a plurality of word lines, the plurality of word lines (within 202; in Fig. 2 related in Figs. 1, 2-5) including a plurality of word lines containing selected memory cells to be erased (see for example in Fig. 3 related in Figs. 1-2, 4-5); circuitry for (e.g., 206; in Fig. 2 related in Figs. 1, 3-5) erasing the selected memory cells in an erase operation (see for example in Fig. 3 related in Figs. 1-2, 4-5), during the erase operation, the circuitry being configured to; apply at least one erase pulse to the memory block to erase the selected memory cells (see for example in Figs. 1, 3-4 related in Figs. 2,5); suspend the at least one erase pulse for a suspend duration (see for example in Figs. 1, 3-4 related in Figs. 2,5); and after the suspend duration and before applying a next erase pulse to the memory block (see for example in Figs. 1, 3-4 related in Figs. 2,5), perform an erase-verify operation on only a portion of the selected memory cells (see for example in Figs. 1, 3-4 related in Figs. 2,5).
However, Shukla is silent with regard to a plurality of selected word lines containing selected memory cells.
In the same field of endeavor, Zhao, for example in Figs. 1-21, discloses a plurality of selected word lines containing selected memory cells (implied the step of 1300-1302; in Fig. 21 related in Figs. 1-20 and also see Abstract).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Shukla such as memory systems with flexible erase suspend-resume operations, and associated systems, devices, and methods (see for example in Figs. 1-5 of Shukla) by incorporating the teaching of Zhao such as memory apparatus and method of operation using adapted erase time compensation for segmented erase (see for example in Figs. 1-21 of Zhao), for the purpose of controlling the applying a word line erase voltage to selected ones of the word lines to encourage erasing of the memory cells coupled to the selected ones of the word lines in the segmented erase operation (Zhao, see Abstract).
For apparatus claims 8-15, MPEP 2112.01(I) instructs examiners, “When the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed inherent.” Shukla et al. and Zhao et al. disclose an identical memory apparatus; the recited functions are presumed inherent. See also, MPEP Foreword (“[T]he Manual contains instructions to examiners, as well as other material in the nature of information and interpretation, and outlines the current procedures which the examiners are required or authorized to follow in appropriate cases in the normal examination of a patent application.”).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device does not possess the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicants are reminded that argument of counsel is not evidence (see MPEP 2145(I)). Applicants are reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 9, the above Shukla/Zhao, the combination discloses wherein: during the step of performing the erase-verify operation on only the portion of the selected memory cells (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above), the circuitry counts the number of memory cells that fail the erase-verify operation to establish a count and determines an erase pulse duration for the next erase pulse as a function of the count (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above).
Regarding claim 10, the above Shukla/Zhao, the combination discloses wherein while determining the erase pulse duration for the next erase pulse as a function of the count (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above), the circuitry: compares the count to a predetermined threshold, and sets the erase pulse duration at a first timeframe in response to the count being above the predetermined threshold (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above), and sets the erase pulse duration at a second timeframe in response to the count being below the predetermined threshold, and wherein the second timeframe is less than the first timeframe (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above).
Regarding claim 11, the above Shukla/Zhao, the combination discloses wherein the portion of selected memory cells includes the memory cells of a single string of a plurality of strings in the memory block (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above), and wherein in response to the single string of memory block passing the erase-verify operation, then the circuitry verifies the remaining strings of the memory block (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above).
Regarding claim 12, the above Shukla/Zhao, the combination discloses wherein in response to any of the remaining strings of the memory block failing the erase-verify operation (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above), then the circuitry sets the erase pulse duration at a third timeframe that is less than the second timeframe (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above).
Regarding claim 13, the above Shukla/Zhao, the combination discloses wherein the portion of selected memory cells includes the memory cells of a single string of a plurality of strings in the memory block (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above).
Regarding claim 14, the above Shukla/Zhao, the combination discloses wherein the plurality of selected word lines include all of the data word lines in the memory block (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above).
Regarding Independent Claim 15, Shukla, for example in Figs. 1-5, discloses an apparatus (see for example in Fig. 2 related in Figs. 1, 3-5), comprising: a memory block (e.g., block 228; in Fig. 2 related in Figs. 1, 3-5) with an array of memory cells (e.g., memory cells 222; in Fig. 2 related in Figs. 1, 3-5) that are arranged in a plurality of word lines (within block 228; in Fig. 2 related in Figs. 1. 3-5), the plurality of word lines including a plurality of word lines containing selected memory cells to be erased (see for example in Figs. 1, 3-4 related in Figs. 2, 5, as discussed above); an erasing means for erasing the selected memory cells in an erase operation (see for example in Figs. 1, 3-4 related in Figs. 2, 5, as discussed above), during the erase operation, the erasing means being configured to; apply at least one erase pulse to the memory block to erase the selected memory cells (see for example in Figs. 1, 3-4 related in Figs. 2, 5, as discussed above); suspend the at least one erase pulse for a suspend duration (see for example in Figs. 1, 3-4 related in Figs. 2, 5 , as discussed above); and after the suspend duration and before applying a next erase pulse to the memory block (see for example in Figs. 1, 3-4 related in Figs. 2, 5, as discussed above), perform an erase-verify operation on only a portion of the selected memory cells (see for example in Figs. 1, 3-4 related in Figs. 2, 5, as discussed above).
However, Shukla is silent with regard to a plurality of selected word lines containing the selected memory cells.
In the same field of endeavor, Zhao, for example in Figs. 1-21, discloses a plurality of selected word lines containing selected memory cells (implied the step of 1300-1302; in Fig. 21 related in Figs. 1-20 and also see Abstract).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Shukla such as memory systems with flexible erase suspend-resume operations, and associated systems, devices, and methods (see for example in Figs. 1-5 of Shukla) by incorporating the teaching of Zhao such as memory apparatus and method of operation using adapted erase time compensation for segmented erase (see for example in Figs. 1-21 of Zhao), for the purpose of controlling the applying a word line erase voltage to selected ones of the word lines to encourage erasing of the memory cells coupled to the selected ones of the word lines in the segmented erase operation (Zhao, see Abstract).
For apparatus claims 16-20, MPEP 2112.01(I) instructs examiners, “When the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed inherent.” Shukla et al. and Zhao et al. disclose an identical memory apparatus; the recited functions are presumed inherent. See also, MPEP Foreword (“[T]he Manual contains instructions to examiners, as well as other material in the nature of information and interpretation, and outlines the current procedures which the examiners are required or authorized to follow in appropriate cases in the normal examination of a patent application.”).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device does not possess the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicants are reminded that argument of counsel is not evidence (see MPEP 2145(I)). Applicants are reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 16, the above Shukla/Zhao, the combination discloses wherein: while performing the erase-verify operation on only the portion of the selected memory cells (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above), the erasing means counts the number of memory cells that fail the erase-verify operation to establish a count and determines an erase pulse duration for the next erase pulse as a function of the count (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above).
Regarding claim 17, the above Shukla/Zhao, the combination discloses wherein while determining the erase pulse duration for the next erase pulse as a function of the count (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above), the erasing means: compares the count to a predetermined threshold, and sets the erase pulse duration at a first timeframe in response to the count being above the predetermined threshold (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above), and sets the erase pulse duration at a second timeframe in response to the count being below the predetermined threshold, and wherein the second timeframe is less than the first timeframe (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above).
Regarding claim 18, the above Shukla/Zhao, the combination discloses wherein the portion of selected memory cells includes the memory cells of a single string of a plurality of strings in the memory block (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above), and wherein in response to the single string of memory block passing the erase-verify operation, then the erasing means verifies the remaining strings of the memory block (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above).
Regarding claim 19, the above Shukla/Zhao, the combination discloses wherein in response to any of the remaining strings of the memory block failing the erase-verify operation (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above), then the erasing means sets the erase pulse duration at a third timeframe that is less than the second timeframe (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above).
Regarding claim 20, the above Shukla/Zhao, the combination discloses wherein the portion of selected memory cells includes the memory cells of a single string of a plurality of strings in the memory block (see for example in Figs. 1, 3-4 related in Figs. 2, 5 of Shukla and also see in Figs. 1-21 of Zhao, as discussed above).
Applicant are reminded that when presenting amendments to claims. In order to be fully responsive, an attempt should be made to point out the patentable novelty (see MPEP 714.04). Additionally, Applicant should point out where and/or how the originally filed disclosure supports the amendment(s) (see MPEP 2163 (II)(A)).
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 11/15/2025