DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/29/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract and title are consistent with the requirements set forth in the MPEP 608.01(b) and 606, respectively.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3, 7-8, 10, are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3-4, 7, 14-15 and 18 of U.S. Patent No. 12,027,460. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of the current application is broader than and anticipated by claim 18 (claim 14-18) of patent no. 12,027,460. Claims 2-3, 7-8 and 10 are similar to and also unpatentable over claims 15, 3-4 and 7 of patent no. 12,057,460. See claim to claim matching in table 1 below.
Current Application
Patent No. 12,027,460
1. A memory device, comprising: blocks horizontally extending in parallel in a first direction, the blocks individually comprising tiers respectively including conductive material and insulative material vertically neighboring the conductive material; strings of memory cells vertically extending through the blocks; and slot structures horizontally alternating with the blocks in a second direction orthogonal to the first direction, the slot structures respectively comprising: insulative liner material substantially covering opposing sidewalls of two of the blocks; and semiconductive granules respectively horizontally extending, in the second direction, from and between opposing portions of the insulative liner material.
14. A memory device, comprising: a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure; strings of memory cells vertically extending through the stack structure, a first material contacting sidewalls of the second insulative liner material, at least some of the first material comprising grains extending from a first sidewall of the second insulative liner material to a second, opposing sidewall of the second insulative liner material.
18. The memory device of claim 14, wherein the first material comprises a semiconductive material.
2. The memory device of claim 1, wherein the semiconductive granules of respective ones of the slot structures comprise: a semiconductive granule at a vertical position; and an additional semiconductive granule at an additional vertical position offset from the vertical position.
15. The memory device of claim 14, wherein the first material further comprises additional grains having a dimension less than a dimension of the grains.
3. The memory device of claim 1, wherein, for respective ones of the slot structures, different ones of the semiconductive granules thereof have different magnitudes of surface area contact with the opposing portions of the insulative liner material than one another.
15. The memory device of claim 14, wherein the first material further comprises additional grains having a dimension less than a dimension of the grains.
7. The memory device of claim 1, wherein the semiconductive granules comprise one or more of Si and Ge.
3. The microelectronic device of claim 1, wherein the grains of the material comprise silicon and germanium.
8. The memory device of claim 7, wherein the semiconductive granules respectively comprise: at least 10 atomic percent Si; and at least 65 atomic percent Ge.
4. The microelectronic device of claim 1, wherein the grains of the material comprise at least about 70 atomic percent germanium.
10. The memory device of claim 1, wherein the slot structures respectively further comprise additional semiconductive granules respectively in physical contact with only one of the opposing portions of the insulative liner material.
7. The microelectronic device of claim 1, wherein the grains of the material further comprises second grains having a smaller dimension than the first grains, the second grains individually contacting only one sidewall of the insulative liner material.
Table 1
Allowable Subject Matter
Claims 4-6 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and/or a timely filed terminal disclaimed filed in response to the double patenting rejection of the independent claim.
The following is a statement of reasons for the indication of allowable subject matter:
the closest art, not considered as prior art, Tapias et al. US PGPub. 2021/0050364, fig. 10-11 or any prior arts of record taken alone or in combination neither anticipates nor renders obvious a memory device wherein “for respective ones of the slot structures, the insulative liner material includes: two side portions substantially covering the opposing sidewalls of the two of the blocks; and a lower portion horizontally extending in the second direction from and between the two side portions” as recited in claim 4 in combination with the “semiconductive granules respectively horizontally extending, in the second direction, from and between opposing portions of the insulative liner material” as recited in claim 1; a memory device wherein “for respective ones of the slot structures, at least one of the semiconductive granules thereof has a different volume than at least one other of the semiconductive granules thereof” as recited in claim 6 in combination with the “semiconductive granules respectively horizontally extending, in the second direction, from and between opposing portions of the insulative liner material” as recited in claim 1; and a memory device wherein “the semiconductive granules are respectively doped with one or more of B, P, and As” as recited in claim 9 in combination with the “semiconductive granules respectively horizontally extending, in the second direction, from and between opposing portions of the insulative liner material” as recited in claim 1. Claim 5 is also objected to as allowable for further limiting and depending upon allowable claim 4.
Claims 11-20 are allowed.
The following is an examiner’s statement of reasons for allowance: the closest art, not considered as prior art, Tapias et al. US PGPub. 2021/0050364, fig. 10-11 or any prior arts of record taken alone or in combination neither anticipates nor renders obvious a non-volatile memory device comprising “a slot structure horizontally interposed between the two blocks and comprising: insulative liner material,” “insulative fill material,” and “non-insulative granules respectively embedded within the insulative fill material, one or more of the non-insulative granules individually in physical contact with each of the first side portion and the second side portion of the insulative liner material” as recited in claim 11; and a 3D NAND Flash memory device comprising “slot structures horizontally alternating with the blocks and respectively comprising: insulative liner material,” “ insulative fill material,” and “grains of non-insulative material embedded in the insulative fill material and respectively horizontally extending from and between the opposing inner side surfaces of the insulative liner material” as recited in claim 16. Claims 12-15 and 17-20 are also allowed for further limiting and depending upon allowed claims 11 and 16.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892