5/DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein a top surface of the bit line contact is at a first height, a top surface of the isolated plug structure is at a second height, a bottom surface of the bit line contact is at a third height, wherein the second height is between the first height and the third height”, as recited in claim 5.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4 and 7-19 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (CN 115472610 A, hereinafter refer to Zhang) in view of Lee (KR 2023-0068137 A, hereinafter refer to Lee).
CN 115472610 A (hereinafter refer to Zhang) is relied upon solely for the English language translation of CN 115472610 A.
KR 2023-0068137 A (hereinafter refer to Lee) is relied upon solely for the English language translation of KR 2023-0068137 A.
Regarding Claim 1: Zhang discloses a semiconductor structure (see Zhang, Fig.9 as shown below and abstract), comprising:
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a substrate (110) comprising a first region (110A) and a second region (110B), the second region (110B) comprising an isolation structure (120) (see Zhang, Fig.9 as shown above);
a plurality of plug structures (215/163/221) disposed on the first region (110A) and the second region (110B) and comprising at least an isolated plug structure (215) disposed on the isolation structure (120) in the second region (110B) (see Zhang, Fig.9 as shown above);
an insulating structure (223) between plug structures (215), wherein a portion of the insulating structure (223) on the isolated plug structure (215) comprises a recess (see Zhang, Fig.9 as shown above);
a capacitor structure (not shown) disposed on the plug structures (163/221) on the first region (110A) (see Zhang, Fig.9 as shown above and pages.8-9).
Zhang is silent upon explicitly disclosing wherein a filling material layer in the recess; and
wherein a portion of the filling material layer and a portion of the capacitor structure are made of a same material.
For support see Lee, which teaches wherein a filling material layer (630/670/680/690) in the recess (see Lee, Figs.39-41 as shown below and abstract); and
wherein a portion of the filling material layer (630/670/680/690) and a portion of the capacitor structure (670/680/690) are made of a same material (see Lee, Figs.39-41 as shown below and abstract).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Zhang and Lee to enable Zhang’s capacitor structure (not shown) disposed on the plug structures to be formed by disposing the filling material layer in the recess, wherein a portion of the filling material layer and a portion of the capacitor structure are made of a same material as taught by Lee in order to improve electric characteristics.
Regarding Claim 2: Zhang as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Zhang and Lee further teaches wherein at least one of the plug structures (215) is disposed on an edge of the isolation structure (120) (see Zhang, Fig.9 as shown above).
Regarding Claim 3: Zhang as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Zhang and Lee further teaches wherein bottom portions of the insulating structure (223) on the isolation structure are at different depths in the isolation structure (120) (see Zhang, Fig.9 as shown above).
Regarding Claim 4: Zhang as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Zhang and Lee further teaches wherein a bit line (BL, not shown) disposed on the substrate and extending from the first region to the second region (see Zhang, Fig.9 as shown above and page.6); and
a bit line contact (BLC, not shown) disposed on the second region and in direct contact with a line end of the bit line (see Zhang, Fig.9 as shown above and page.6).
Regarding Claim 7: Zhang as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Zhang and Lee further teaches wherein the capacitive structure (705) comprises: a plurality of bottom electrodes (665) (see Lee, Figs.39-41 as shown above);
a capacitive dielectric layer (675) covering along surfaces of the bottom electrodes (665) (see Lee, Figs.39-41 as shown above); and
a top electrode layer (685) disposed on the capacitive dielectric layer (675) (see Lee, Figs.39-41 as shown above).
Regarding Claim 8: Zhang as modified teaches a semiconductor structure as set forth in claim 7 as above. The combination of Zhang and Lee further teaches wherein a portion of the filling material layer (630/670/680/690) comprises a same material as the capacitive dielectric layer (675/670) (see Lee, Figs.39-41 as shown above).
Regarding Claim 9: Zhang as modified teaches a semiconductor structure as set forth in claim 7 as above. The combination of Zhang and Lee further teaches wherein a portion of the filling material layer (630/670/680/690) comprises a same material as the top electrode layer (680) (see Lee, Figs.39-41 as shown above).
Regarding Claim 10: Zhang as modified teaches a semiconductor structure as set forth in claim 7 as above. The combination of Zhang and Lee further teaches wherein the filling material layer (630/670/680/690) has a multilayer structure (see Lee, Figs.39-41 as shown above).
Regarding Claim 11: Zhang as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Zhang and Lee further teaches wherein a bottom surface of the recess is higher than a top surface of the isolated plug structure (215) (see Zhang, Fig.9 as shown above).
Regarding Claim 12: Zhang as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Zhang and Lee further teaches wherein a plurality of landing pads (195) on the plug structures (161) on the first region (110A), respectively, wherein the insulating structure (223) comprises insulating walls between the plug structures (215) and insulating pads (a portion of plug 215) between the landing pads (195) (see Zhang, Fig.9 as shown above),
wherein a lowest portion of the filling material layer (630/670/680/690) is lower than bottom surfaces of the insulating pads (380) (see Lee, Figs.39-41 as shown above).
Regarding Claim 13: Zhang discloses a semiconductor structure (see Zhang, Fig.9 as shown above and abstract), comprising:
a substrate (110), comprising an isolation structure (120) and a plurality of active regions (181) defined by the isolation structure (120) (see Zhang, Fig.9 as shown above and abstract);
a plurality of plug structures (215/161/221) disposed on the substrate (110), comprising first plug structures (161/221) disposed on active regions and second plug structures (215) disposed on the isolation structure (120), wherein the first plug structures (161/221) are in direct contact with the active regions (181), and top surfaces of the second plug structures (215) are lower than top surfaces of the first plug structures (161/221) (see Zhang, Fig.9 as shown above and abstract);
a dielectric layer (147) between the isolation structure (120) and the second plug structures (215) (see Zhang, Fig.9 as shown above and abstract);
a capacitor structure (not shown) disposed on the first plug structures (161/221) (see Zhang, Fig.9 as shown above and pages.8-9);
an insulating structure (223) between the plug structures (215), wherein a portion of the insulating structure (223) on the second plug structures (215) comprises a recess (see Zhang, Fig.9 as shown above and pages.8-9).
Zhang is silent upon explicitly disclosing wherein a filling material layer disposed in the recess, wherein a portion of the filling material layer comprises a same material as the capacitor structure.
For support see Lee, which teaches wherein a filling material layer (630/670/680/690) disposed in the recess, wherein a portion of the filling material layer (630/670/680/690) comprises a same material as the capacitor structure (670/680/690) (see Lee, Figs.39-41 as shown above and abstract).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Zhang and Lee to enable Zhang’s capacitor structure (not shown) disposed on the plug structures to be formed by disposing the filling material layer in the recess, wherein a portion of the filling material layer comprises a same material as the capacitor structure as taught by Lee in order to improve electric characteristics.
Regarding Claim 14: Zhang as modified teaches a semiconductor structure as set forth in claim 13 as above. The combination of Zhang and Lee further teaches wherein the capacitor structure (670/680/690) comprises: a plurality of bottom electrodes (660) (see Lee, Figs.39-41 as shown above and abstract);
a capacitive dielectric layer (670) covering along surfaces of the bottom electrodes (660) (see Lee, Figs.39-41 as shown above and abstract); and
a top electrode layer (680) disposed on the capacitive dielectric layer (670) (see Lee, Figs.39-41 as shown above and abstract).
Regarding Claim 15: Zhang as modified teaches a semiconductor structure as set forth in claim 14 as above. The combination of Zhang and Lee further teaches wherein a portion of the filling material layer (630/670/680/690) comprises a same material as the capacitive dielectric layer (670) (see Lee, Figs.39-41 as shown above).
Regarding Claim 16: Zhang as modified teaches a semiconductor structure as set forth in claim 14 as above. The combination of Zhang and Lee further teaches wherein a portion of the filling material layer (630/670/680/690) comprises a same material as the top electrode layer (680) (see Lee, Figs.39-41 as shown above).
Regarding Claim 17: Zhang as modified teaches a semiconductor structure as set forth in claim 14 as above. The combination of Zhang and Lee further teaches wherein the filling material layer (630/670/680/690) has a multilayer structure (see Lee, Figs.39-41 as shown above).
Regarding Claim 18: Zhang as modified teaches a semiconductor structure as set forth in claim 13 as above. The combination of Zhang and Lee further teaches wherein a bottom surface of the recess is higher than a top surface of the second plug structures (215) (see Zhang, Fig.9 as shown above).
Regarding Claim 19: Zhang as modified teaches a semiconductor structure as set forth in claim 13 as above. The combination of Zhang and Lee further teaches wherein a plurality of landing pads (195) on the first plug structures (161/221), respectively, wherein the insulating structure (223) comprises insulating walls between the first plug structures (161/331) and insulating pads (a portion of plug 215) between the landing pads (195) (see Zhang, Fig.9 as shown above),
wherein a lowest portion of the filling material layer (630/670/680/690) is lower than bottom surfaces of the insulating pads (380) (see Lee, Figs.39-41 as shown above).
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (CN 115472610 A, hereinafter refer to Zhang) and Lee (KR 2023-0068137 A, hereinafter refer to Lee) as applied to claim 4 above and further in view of Zhang (CN 116056453 A, hereinafter refer to Zhang ‘453).
CN 115472610 A (hereinafter refer to Zhang) is relied upon solely for the English language translation of CN 115472610 A.
KR 2023-0068137 A (hereinafter refer to Lee) is relied upon solely for the English language translation of KR 2023-0068137 A.
CN 116056453 A (hereinafter refer to Zhang ‘453) is relied upon solely for the English language translation of CN 116056453 A.
Regarding Claim 6: Zhang as modified teaches a semiconductor structure as applied to claim 4 above. The combination of Zhang and Lee is silent upon explicitly disclosing wherein a farthest distance from the plug structures to the first region is larger than a distance from the line end of the bit line to the first region.
For support see Zhang ‘453, which teaches wherein a farthest distance from the plug structures (50) to the first region (R2) is larger than a distance from the line end of the bit line to the first region (R2) (see Zhang ‘453, Figs.13-14 and abstract).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Zhang, Lee, and Zhang ‘453 to enable the combination of Zhang and Lee farthest distance from the plug structures to the first region to be larger than a distance from the line end of the bit line to the first region as taught by Zhang ‘453 in order to obtain the conductive plug with large size to reduce the resistance, and ensure the electrical isolation between the conductive plug.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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