Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Khalil et al. (US 11,923,424, hereinafter Khalil).
Regarding claim 1, Figures 4-10A of Khalil disclose a method of fabricating a high electron mobility transistor, comprising: providing a substrate 102 having a semiconductor channel layer 106, a semiconductor barrier layer 108, and a passivation layer 130 disposed thereon; forming a gate field plate 150 (portions of 150 overlying 130) and at least one first field plate 160, wherein the gate field plate 150 and the at least one first field plate 160 are laterally spaced apart from each other, and the step of forming the gate field plate 150 and the at least one first field plate 160 comprises: forming a conformal first metal layer on a surface of the passivation layer and patterning the conformal first metal layer (col. 13, lines 44-47); forming a first interlayer dielectric layer 170, conformally covering the gate field plate and the at least one first field plate; and forming a source electrode 185 and a second field plate 180, wherein the second field plate 180 conformally covers the first interlayer dielectric layer 170 and extends over the gate field plate 150 and the at least one first field plate 160, a top surface of the second field plate comprises a first portion and a second portion (see annotated Fig. 10A below), which are disposed directly above the gate field plate and the at least one first field plate, respectively, and a third portion (see annotated Fig. 10A below), which is disposed directly above a gap between the gate field plate and the at least one first field plate, and the first portion and second portion of the top surface of the second field plate are higher than the third portion of the top surface of the second field plate (see annotated Fig. 10A below).
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Regarding claim 2, Figures 4-10A of Khalil disclose the method of fabricating the high electron mobility transistor of claim 1, wherein the passivation layer 130 comprises a gate contact hole (hole in which gate electrode 150 resides), and a portion of the conformal first metal layer fills in the gate contact hole (col. 13, lines 44-47 discloses the conformal deposition process which would inherently result in the conformal layer deposited in the gate contact hole).
Regarding claim 3, Figures 4-10A of Khalil disclose the method of fabricating the high electron mobility transistor of claim 1, wherein the step of forming the source electrode 185 and the second field plate 180 comprises: forming a conformal second metal layer on a surface of the first interlayer dielectric layer 170; and patterning the conformal second metal layer (col. 15, lines 23-27).
Regarding claim 5, Figures 4-10A of Khalil disclose the method of fabricating the high electron mobility transistor of claim 1, wherein: the at least one first field plate 160 is electrically connected to the source electrode 185 (col. 9, lines 53-57); and the second field plate 180 is electrically connected to the source electrode 185 (col. 8, lines 39-41).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Khalil.
Regarding claim 4, Khalil discloses in Fig. 1 and 10A the second field plate 180 is longer than a sum of the length of the gate field plate 150 and the first field plate 160. Khalil does not show a top view of the device, so it does not specifically disclose the area of the second field plate is larger than a sum of the area of the gate field plate and the first field plate when perceived from a top-down perspective. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the area of the second field plate larger than a sum of the area of the gate field plate and the first field plate when perceived from a top-down perspective, since doing so would increase the surface area of the electrode and increase the field reduction potential.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW C LANDAU whose telephone number is (571)272-1731. The examiner can normally be reached M-F, 9:30-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MATTHEW C. LANDAU
Supervisory Patent Examiner
Art Unit 2891
/MATTHEW C LANDAU/ Supervisory Patent Examiner, Art Unit 2891
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