DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
3. Claim(s) 1, 5-9, is/are rejected under 35 U.S.C. 103 as being unpatentable over Oka et al., US 2010/0133681 A1.
Claims 1, 7-9. Oka et al., disclose a semiconductor module (such as the one in figs. 1-2, comprising:
-a mounting board (item 3);
-a semiconductor chip mounted (item 5) on the mounting board;
-a tubular support conductor (item 1) mounted on the mounting board;
-a housing part (item 20) that accommodates the mounting board, the semiconductor chip, and the support conductor;
-a connection terminal (item 9) electrically connected to the semiconductor chip, the connection terminal including a first end portion press-fitted into the support conductor and a second end portion protruding from the housing part (as seen in the structure of fig. 1);
-and a conductive first joining part located between an inner wall surface of the support conductor and an outer wall surface of the connection terminal, and configured to join between the support conductor and the connection terminal.
In the embodiment of figs. 1 and 2, Oka appears not to explicitly disclose all the limitations as in claim 1 (for example, a conductive first joining part located between an inner wall surface of the support conductor and an outer wall surface of the connection terminal, and configured to join between the support conductor and the connection terminal).
However, in other embodiments (such as the embodiment of figs. 8-9) Oka [0078] discloses: in the present embodiment, a printed circuit board (not shown) is used as the external wiring to be connected to the external terminals. For example, in the case where the external terminals are pressed against, and joined to, pad portions of the printed circuit board, the third external terminals 12a or the fourth external terminals 12b are used. Also, in the case where the external terminals are joined, by soldering, to through holes of the printed circuit board, the fifth external terminals 12c are used. Further, in the case where the external terminals are connected to the through holes of the printed circuit board by press-in connection, the sixth external terminals 12d are used.
To improve quality of a semiconductor module device, it would have been obvious to one of ordinary skill in the art at the time of invention to use Terminal connections in semiconductor modules to ensure stable electrical paths, withstand operational stresses, manage heat, protect against environmental damage, integrate with control systems, and enable modular design. Without reliable terminal connections, even the most advanced semiconductor dies would be prone to failure in real-world conditions.
Claim 5. Oka et al., disclose the semiconductor module according to claim 1, wherein the housing part includes: a casing (item 20] enclosing the mounting board, the semiconductor chip, and the support conductor; and a sealing body filled in an internal space of the casing, and the sealing body is softer than the casing.
Claim 6. Oka et al., disclose the semiconductor module according to claim 1, wherein the connection terminal includes a part including the first end portion, the first joining part is formed on the part including the first end portion, and the second end portion is exposed from the first joining part (as seen in the structure of fig. 1).
4. Claim(s) 2-4, is/are rejected under 35 U.S.C. 103 as being unpatentable over Oka et al., US 2010/0133681 A1, in view of ASADA et al., US 20220254749 A1.
Claims 2-4. Oka et al., disclose the semiconductor module according to claim 1, above.
Oka appears to not disclose “wherein a solidus temperature of the first joining part is above a maximum environmental temperature at which the semiconductor module is used”.
In a similar method of manufacturing semiconductor module device, [0036] of ASADA et al., indicate for example, in Step S1, the plate solder as the bonding material 2a is heated to a temperature exceeding the melting point to melt, and then cured to bond the base portion 1 and the semiconductor element 3. Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have formed the Oka semiconductor module by using the melting point process of ASADA et al., to ensure that the metal is in a fully liquid state, allowing it to flow and fill the mold properly.
Allowable Subject Matter
5. Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
(A) Claim 10, contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of an inspection process of inspecting the semiconductor module in a heated state, wherein the joining process comprises a process of melting and solidifying the joining material by heating the semiconductor module in the inspection process.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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