DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In particular, regarding the recitation “the second conductive section is located between the first and third conductive sections and connected to the outer lead of the first conductive section and the third conductive section” on lines 7 – 9, it is unclear as to whether the second conductive section is connected to the outer lead of the third conductive section, or whether the second conductive section is connected to the third conductive section. There is no previous recitation of the third conductive section including an outer lead, thus Examiner is assuming that the second conductive section is merely conducted to the third conductive section (and not the outer lead of the third conductive section).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ban et al. (U.S. Patent Publication No. 2008/0116546).
Regarding claim 1, in Figure 11, Bang discloses a circuit board comprising: a substrate (100) having a surface, a first area (area right of die pad 10), a second area and (middle area containing the die pad 10) a third area (area left of die pad 10) are defined on the surface, and the second area is located between the first and third areas in a first direction for transporting the circuit board (Figure 11); a plurality of circuit lines each including a first conductive section (20, 30) arranged on the first area, a second conductive section (210) arranged on the second area and a third conductive section (20, 30, unlabeled) arranged on the third area, the first conductive section includes an inner lead (20) and an outer lead (30), the second conductive section is located between the first and third conductive sections (Figure 11) and connected to the outer lead of the first conductive section (via inner lead 20) and the third conductive section (Figure 11); and a protective layer (41, 51, 44, 54) configured to cover the first and third conductive sections, wherein the second conductive section, the inner lead and the outer lead of the first conductive section are not covered by the protective layer(Figure 11).
Regarding claim 2, Bang discloses wherein the protective layer includes a first protective portion, at least one second protective portion and a hollow portion which is located between the first protective portion and the at least one second protective portion, the first protective portion is configured to cover the first conductive section, the inner lead and the outer lead of the first conductive section are not covered by the first protective portion, the at least one second protective portion is configured to cover the third conductive section, the hollow portion is configured to expose the outer lead of the first conductive section and the second conductive section, a predetermined cutting line is configured to run through the hollow portion and be located between the first protection portion and the at least one second protective portion to separate the circuit board into a part to be reserved and a part to be removed, the outer lead is located between the first protective portion and the predetermined cutting line, the first conductive section and the first protective portion covering the first conductive section are located on the part to be reserved, the second conductive section, the third conductive section and the at least one second protective portion covering the third conductive section are located on the part to be removed (Figure 11).
Regarding claim 3, Bang discloses wherein a test pad of the third conductive section is not covered by the at least one second protective portion (Figure 11).
Regarding claim 4, Bang discloses wherein the protective layer includes two second protective portions, and the first protective portion is located between the two protective portions (Figure 11).
Regarding claim 5, Bang discloses wherein a first distance between the first protective portion and the at least one second protective portion along the first direction is greater than or equal to 0.5 µm and less than or equal to 2 µm (Figure 11).
Regarding claim 6, Bang discloses wherein a test pad of the third conductive section is not covered by the at least one second protective portion, a second distance between the at least one second protective portion and an end of the test pad along the first direction is greater than or equal to 0.5 µm and less than or equal to 2 µm (Figure 11).
Regarding claim 7, Bang discloses wherein the at least one second protective portion extends along a second direction intersecting the first direction (Figure 11).
Regarding claim 8, Bang discloses wherein the at least one second protective portion includes a plurality of protrusions, a third distance between the adjacent protrusions along a second direction intersecting the first direction is greater than or equal to 0.5 µm and less than or equal to 158 mm (Figure 11).
Regarding claim 9, Bang discloses wherein a fourth distance between the adjacent protrusions along the first direction is greater than or equal to 0.5 µm and less than or equal to 50 mm (Figure 11).
Regarding claim 10, Bang discloses wherein the at least one second protective portion includes a plurality of protrusions, and a fourth distance between the adjacent protrusions along the first direction is greater than or equal to 0.5 µm and less than or equal to 50 mm (Figure 11).
Regarding claim 11, Bang discloses wherein the at least one second protective portion includes a plurality of protrusions, and a fourth distance between the adjacent protrusions along the first direction is greater than or equal to 0.5 µm and less than or equal to 50 mm (Figure 11).
Regarding claim 12, Bang discloses wherein a top surface and a lateral surface of the third conductive section are covered by the at least one second protective portion, the surface of the substrate where is between the third conductive sections of the adjacent circuit lines are covered by the at least one second protective portion, a thickness of the at least one second protective portion covering the top surface of the third conductive section is greater than or equal to 0.5 µm and less than or equal to 50 µm (Figure 11).
Regarding claim 13, Bang discloses wherein each of the plurality of circuit lines includes a copper layer and a tin layer which is located between the copper layer and the at least one second protective portion (Figure 11).
Regarding claim 14, Bang discloses wherein a first edge of the at least one second protective portion is closer to the first protective portion than a second edge of the at least one second protective portion, a fifth distance from the first edge to the second edge is greater than or equal to 0.5 µm and less than or equal to 50 mm (Figure 11).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST.
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TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847