DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al (US 2021/0273167 A1).
Regarding claim 1, Liu et al discloses a cover glass bonding method (Figures 1A, 2B and 2), the method comprising: aligning (Figure 1A, reference 101) each wafer (Figure 1A, references 108 and 116) of a set of organic light-emitting diode (paragraph 0014) on silicon (OLEDoS) wafers (paragraph 0027) and disposing the set of OLEDoS wafers (Figure 1A, reference 122) on an upper table vacuum assembly system (VAS) module of a VAS device (Figures 1A, 1B reference 110) without using a carrier glass; disposing an epoxy-drawn cover glass on a lower table VAS module of the VAS device (paragraph 0022); bonding the set of OLEDoS wafers and the epoxy-drawn cover glass (paragraph 0025 and 0044), wherein a working position of each wafer of the set of OLEDoS wafers is individually controlled in the upper table VAS module of the VAS device (Figure 2, reference 204; (paragraph 0024).
Allowable Subject Matter
Claims 2 and 3 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art does not disclose nor fairly suggest a cover glass bonding method, the method comprising: wherein: the set of OLEDoS wafers includes first, second, third, and fourth wafers, each of the first, second, third, and fourth wafers has a circular shape having a diameter of about 300 mm, the epoxy-drawn cover glass has a square shape having a size of about 650 mm x 750 mm, the first and second wafers have first and second notches arranged side by side on an upper portion of the set of OLEDoS wafers in a first row, and the third and fourth wafers have third and fourth notches arranged side by side on a lower portion of the set of OLEDoS wafers in a second row, and the third and fourth notches are arranged to the first and second notches in a straight line to bond the set of OLEDoS wafers and the epoxy-drawn cover glass (claim 2), further incorporated into the independent claim and in the context of its recited process, along with its depending claims.
Claims 4-20 are allowed over the prior art of record.
The following is an examiner’s statement of reasons for allowance: The prior art does not disclose nor fairly suggest bonding system of a cover glass comprising: inverts the set of notch-aligned wafers one time, and transports and places the set of notch-aligned wafers on an upper table vacuum assembly system (VAS) module of a vacuum assembly system (VAS) device; a second transfer module that transports and arranges a cover glass, which is drawn with epoxy in a cover glass preparation stage, to a lower table VAS module of the VAS device; and the VAS device that bonds the epoxy-drawn cover glass and the set of notch-aligned wafers in a vacuum atmosphere, the set of notch-aligned wafers transferred in a first direction in an inverted state by the first transfer module and disposed on the upper table VAS module, the epoxy-drawn cover glass transferred in a direction opposite to the first direction by the second transfer module and disposed on the lower table VAS module (claim 4), a vacuum assembly system (VAS) device for a bonding system for a plurality of organic light-emitting diode on silicon (OLEDoS) wafers and a cover glass, the VAS device comprising: a UVW alignment stage including first, second, third, and fourth UVW alignment stages that are connected to the first, second, third, and fourth upper table wafer stages and independently perform 3-axis UVW alignment on each of the first, second, third, and fourth upper table wafer stages; a vacuum chuck unit including first, second, third, and fourth vacuum chucks that place the first, second, third, and fourth wafers on the first, second, third, and fourth upper table wafer stages, respectively; a vacuum chuck driving unit including first, second, third, and fourth vacuum chuck driving units that elevate and lower the vacuum chuck unit; and first, second, third, fourth, fifth, sixth, seventh and eighth high-resolution vision units provided in pairs for each of the first, second, third, and fourth upper table wafer stages and communicating with a control module so that the UVW alignment stage is adjusted in a 3-axis UVW direction (claim 11) and a control method of a bonding system of a plurality of carrier-free organic light-emitting diode on silicon (OLEDoS) wafers and a cover glass, the method comprising: sequentially arranging first, second, third, and fourth wafers among the wafers to form a set of notch-aligned wafers in case that it is determined that first, second, third, and fourth compartments of an index stage are empty through communication with the index stage of the index stage module; communicating with a first transfer module to take out the set of notch-aligned wafers, to invert the set of notch-aligned wafers one time, and controlling transfer and placement of the set of notch-aligned wafers to an upper table vacuum assembly system (VAS) module of a VAS device; and communicating with a second transfer module and controlling transfer and arrangement of the cover glass drawn with epoxy in a cover glass preparation stage to a lower table VAS module of the VAS device; and controlling the upper table VAS module and the lower table VAS module of the VAS device to bond the set of notch-aligned wafers disposed in the upper table VAS module by the first transfer module in an inverted state in a first direction, and the epoxy-drawn cover glass disposed in the lower table VAS module by the second transfer module in a second direction opposite to the first direction, under a vacuum atmosphere (claim 17) as described in the independent claims and in the context of their recited processes, along with their depending claims
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Takasaki et al (7,988,803 B2) discloses a device and method for joining substrates.
Lee (US 2024/0174560 A1) discloses a glass substrate chemical strengthening furnace apparatus.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA D HARRISON whose telephone number is (571)272-1959. The examiner can normally be reached M-F 7-4:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MONICA D HARRISON/Primary Examiner, Art Unit 2815
mdh
September 3, 2026
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