DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election with traverse of claims 1-10 in the reply filed on 01/26/2026 is acknowledged.
Applicant's election with traverse of Invention I, claims 1-10 in the reply filed on 01/26/2026 is acknowledged. The traversal is on the ground(s) that there is no prima facie foundation for distinctiveness. This is not found persuasive because the inventions claim divergent subject matter which requires divergent prior art searches and considerations, constituting a serious search burden.
The requirement is still deemed proper and is therefore made FINAL.
Claim Objections
Claim(s) 10 is/are objected to because of the following informalities:
Claim(s) 10 recite(s) the recite two fractions that are formatted differently.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 8, and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kamalanathan, US 9524777 B1.
As to claim 1, Kamalanathan discloses a method for erasing a two-terminal memory cell (see Kamalanathan Fig 8), comprising:
select a two-terminal non-volatile memory cell (see Kamalanathan Fig 3) in a set memory cell state (see Kamalanathan Fig 8 Ref 308); perform an erase process on the two-terminal non-volatile memory cell (see Kamalanathan Cols 6-7, Lines 65-7); perform a weak program process on the two-terminal non-volatile memory cell (see Kamalanathan Col 8, Lines 37-55); repeat the erase process and the weak program process an integer: N times, wherein N is larger than one (see Kamalanathan Fig 8 and Col 9, Lines 24-43); and following an Nth erase process and Nth weak program process, terminate the method (see Kamalanathan Fig 8 Ref 816).
As to claim 2, Kamalanathan discloses the method of claim 1, further comprising,
in response to repeating the erase process and the weak program process the integer: N times, perform a read process on the two-terminal non-volatile memory cell (see Kamalanathan Fig 8 Ref 808 and 814), and confirm a current (see Kamalanathan Col 4, Lines 46-58) of the two-terminal non-volatile memory cell is above a first current magnitude defining a reset memory cell state and below a second current magnitude defining the set memory cell state (see Kamalanathan Col 11, Lines 8-22).
As to claim 3, Kamalanathan discloses the method of claim 2, further comprising
confirming the current of the two-terminal non-volatile memory cell is below a third current magnitude defining a weakly set memory cell state and above the first current magnitude (see Kamalanathan Col 8, Lines 37-55 and Cols 11-12, Lines 51-3), wherein
the third current magnitude is smaller than the second current magnitude (see Kamalanathan Fig 6 Refs R1, R3, and R6; V=IR).
As to claim 8, Kamalanathan discloses the method of claim 1, wherein the two-terminal non-volatile memory cell is a filamentary resistive switching memory cell (see Kamalanathan Fig 3).
As to claim 9, Kamalanathan discloses the method of claim 1, wherein
N is a variable integer greater than one (see Kamalanathan Fig 8 and Col 9, Lines 24-43), and the method further comprises: reading a current value (see Kamalanathan Col 4, Lines 46-58) of the two-terminal non-volatile memory cell following the weak program process; comparing the current value to a range of current values associated with a weakly set memory cell state; and one of: terminating the erasing in response to the current value being within the range of current values associated with the weakly set memory cell state; or incrementing a value of N and repeating the erase process and the weak program process an N+1th time (see Kamalanathan Col 11, Lines 8-22).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kamalanathan, US 9524777 B1, in view of Yasuda, US 20110175049 A1.
As to claim 5, Kamalanathan discloses the method of claim 1, wherein
the erase process applies a voltage and current across the two-terminal non-volatile memory cell.
Kamalanathan does not appear to explicitly disclose of about 2.4 volts (V) and a maximum current of about 200 µA.
Yasuda discloses of about 2.4 volts (V) and a maximum current of about 200 µA (see Yasuda Fig 6B and Ref [0093]).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a method, as disclosed by Kamalanathan, may implement a particular voltage application schema, as disclosed by Yasuda. The inventions are well known variants of filamentary memories and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Yasuda’s attempt to improve low current characteristics.
Allowable Subject Matter
Claim(s) 4, 6, 7, and 10 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not appear to disclose (as recited in claim 4):
the first current magnitude is about 1 microamp (µA), the second current magnitude is within a range from about 30 to about 50µA and the third current magnitude is about 10µA.
The prior art does not appear to disclose (as recited in claim 6):
a program process for programming the two-terminal non-volatile memory cell to the set memory cell state has a voltage from about 2.5 to about 3.5 volts and a current from about 300 to about 400 µA, and wherein the weak program process has a second voltage from about 2.5 to about 3.5 volts, and a second current of 100 µA or less.
The prior art does not appear to disclose (as recited in claim 10):
the weak program process applies a low program current to the two-terminal non-volatile memory cell that is about 1/3 to about 1/4 a program current associated with a program process for changing the two-terminal non-volatile memory cell from a reset memory cell state to the set memory cell state; and the range of current values associated with the weakly set memory cell state is greater than 1 µA and less than or equal to 10 µA.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mizuguchi, US 20120294063 A1 discloses a weak program process.
Nazarian US 20140328108 A1 discloses a maximum current of about 200 µA.
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 02/20/2026