DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment
Acknowledgment is made of applicant's Amendment, filed 05-26-2026. The changes and remarks disclosed therein have been considered.
Claim(s) 10 has/have been amended, and claim(s) 1-20 remain(s) pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 8, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kamalanathan, US 9524777 B1.
As to claim 1, Kamalanathan discloses a method for erasing a two-terminal memory cell (see Kamalanathan Fig 10), comprising:
select a two-terminal non-volatile memory cell (see Kamalanathan Fig 3) in a set memory cell state (see Kamalanathan Fig 8 Ref 308); perform an erase process on the two-terminal non-volatile memory cell (see Kamalanathan Cols 10-11, Lines 31-38, and Fig 10 Ref 1010); perform a weak program process on the two-terminal non-volatile memory cell (see Kamalanathan Cols 10-11, Lines 31-38, and Fig 10 Ref 1016); repeat the erase process and the weak program process (see Kamalanathan Col 11, Lines 8-22), and terminate the method (see Kamalanathan Fig 10 Ref 1020).
Kamalanathan does not appear to explicitly disclose an integer: N times, wherein N is larger than one; and following an Nth erase process and Nth weak program process, terminate the method.
However, it would have been obvious to one skilled in the art at the time of the effective filing of the invention that the method disclosed by Kamalanathan, may repeat, one or more times, the erase operation and the wear programing operation the same number of time (see Kamalanathan Col 11, Lines 8-22). The occurrence of a number of repetitions of an erase operation being the same a number repetitions of a weak programming operation is not statistically insignificant, and it would have been obvious to try that particular condition to ensure that the disclosed invention functioned properly (see MPEP 2141.I). Furthermore, the invention fails to claim the critically of the two operations having the same number of reptations (see MPEP 2144.05.I), and further arguments are required to clarify how the invention overcomes it’s obviousness in view of the prior art.
As to claim 2, Kamalanathan discloses the method of claim 1, further comprising,
in response to repeating the erase process and the weak program process the integer: N times, perform a read process on the two-terminal non-volatile memory cell (see Kamalanathan Fig 10 Refs 1014 and 1018), and confirm a current (see Kamalanathan Col 11, Lines 8-38) of the two-terminal non-volatile memory cell is above a first current magnitude defining a reset memory cell state (see Kamalanathan Col 11, Lines 8-22; A reset state is a high resistive state, thus a low current state.) and below a second current magnitude defining the set memory cell state (see Kamalanathan Col 11, Lines 22-38; A set state is a low resistive state, thus a high current state.).
As to claim 3, Kamalanathan discloses the method of claim 2, further comprising
confirming the current of the two-terminal non-volatile memory cell is below a third current magnitude defining a weakly set memory cell state (see Kamalanathan Cols 11-12, Lines 51-3; A “strong” programmed state is a weakly set memory cell state.) and above the first current magnitude (see Kamalanathan Cols 11-12, Lines 51-3; The current of the “weak” programmed state is lesser than the current of the “strong” programmed state.), wherein
the third current magnitude is smaller than the second current magnitude (see Kamalanathan Fig 6 Refs R1, R3, and R6; V=IR).
As to claim 8, Kamalanathan discloses the method of claim 1, wherein the two-terminal non-volatile memory cell is a filamentary resistive switching memory cell (see Kamalanathan Fig 3).
As to claim 9, Kamalanathan discloses the method of claim 1, wherein
N is a variable integer greater than one (see Kamalanathan Col 11, Lines 8-22 and MPEP 2141.I), and the method further comprises: reading a current value (see Kamalanathan Cols 11 and 12, Lines 8-3) of the two-terminal non-volatile memory cell following the weak program process; comparing the current value to a range of current values associated with a weakly set memory cell state; and one of: terminating the erasing in response to the current value being within the range of current values associated with the weakly set memory cell state; or incrementing a value of N and repeating the erase process and the weak program process an N+1th time (see annotated image of Kamalanathan Fig 10 below, Col 11, Lines 8-22 and 22 and MPEP 2141; It is obvious that the “one or more” language disclosed in column 11 may be implemented with highlighted operation below.).
PNG
media_image1.png
220
316
media_image1.png
Greyscale
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kamalanathan, US 9524777 B1, in view of Yasuda, US 20110175049 A1.
As to claim 5, Kamalanathan discloses the method of claim 1, wherein
the erase process applies a voltage and current across the two-terminal non-volatile memory cell.
Kamalanathan does not appear to explicitly disclose of about 2.4 volts (V) and a maximum current of about 200 µA.
Yasuda discloses of about 2.4 volts (V) and a maximum current of about 200 µA (see Yasuda Fig 6B and Ref [0093]).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a method, as disclosed by Kamalanathan, may implement a particular voltage application schema, as disclosed by Yasuda. The inventions are well known variants of filamentary memories and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Yasuda’s attempt to improve low current characteristics.
Response to Arguments
Applicant's arguments filed 05-26-2026 have been fully considered and they are persuasive.
Examiner agrees that Kamalanathan does not explicitly disclose repeating an erase process and an weak program process an integer: N times.
With regards to order of the steps in the claimed method, the steps in claimed method are not claimed to be in a particular order other than the termination step occurring after erasing and weak programming steps, and must be claimed as such to be interpreted as argued.
With regards to a third current, Kamalanathan discloses multiple currents in figure 6, many of which are intermediate the “erase” state and the “weakly set” state. The claim does not require a “weakly set” state to be programmed with a weak program process, and column 11, line 8 through and column 12, line 3 discloses the claimed relationship.
The rejection of claim 9 has been further clarified above.
Allowable Subject Matter
Claim(s) 4, 6, 7, and 10 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not appear to disclose (as recited in claim 4):
the first current magnitude is about 1 microamp (µA), the second current magnitude is within a range from about 30 to about 50µA and the third current magnitude is about 10µA.
The prior art does not appear to disclose (as recited in claim 6):
a program process for programming the two-terminal non-volatile memory cell to the set memory cell state has a voltage from about 2.5 to about 3.5 volts and a current from about 300 to about 400 µA, and wherein the weak program process has a second voltage from about 2.5 to about 3.5 volts, and a second current of 100 µA or less.
The prior art does not appear to disclose (as recited in claim 10):
the weak program process applies a low program current to the two-terminal non-volatile memory cell that is about 1/3 to about 1/4 a program current associated with a program process for changing the two-terminal non-volatile memory cell from a reset memory cell state to the set memory cell state; and the range of current values associated with the weakly set memory cell state is greater than 1 µA and less than or equal to 10 µA.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, RICHARD ELMS can be reached at (517)272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 07/27/2026
Prosecution Insights