Prosecution Insights
Last updated: April 19, 2026
Application No. 18/678,325

PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§103
Filed
May 30, 2024
Examiner
AYCHILLHUM, ANDARGIE M
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electro-Mechanics Co., Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
99%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
899 granted / 1069 resolved
+16.1% vs TC avg
Moderate +15% lift
Without
With
+15.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
10 currently pending
Career history
1079
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
53.7%
+13.7% vs TC avg
§102
33.7%
-6.3% vs TC avg
§112
3.8%
-36.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1069 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statements (IDSs) submitted on 05/30/2024 is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 8-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Watanabe et al. (US 2012/0138336 A1). Pertaining to claim 1, Watanabe et al. discloses A printed circuit board (Abstract), comprising: a first insulating layer (100, see figs. 1A-1B) including a groove portion (110, see figs 1-5). on an upper side (see figs. 1-5); and a first wiring layer (150, see figs. 1A-1C) having an embedded portion embedded in the groove portion (see figs. 1A-2C) and a protruding portion (protruding portion of the circuit pattern 150, see figs. 1-2) protruding onto the first insulating layer (100), wherein the protruding portion of the first wiring layer (150) has a width of a lower end portion (see fig. 1C), narrower than a width of an upper end portion (see fig. 1C). Pertaining to claim 8, Watanabe et al. discloses, wherein a width of the embedded portion is narrower than a width of the protruding portion (see figs. 1-2). Pertaining to claim 9, Watanabe et al. discloses, further comprising: a second wiring layer (120, see fig. 1-2) disposed below the first wiring layer (150), and spaced apart from the first wiring layer (150). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2-6 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe et al. (US 2012/0138336 A1) in view of Furutani (US 2023/0171889 A1). Pertaining to claim 2, Watanabe et al. discloses, wherein the first wiring layer (150) comprises a first metal layer (120, see figs. 1A-1B) disposed on an inner wall of the groove portion (110) and extending along a portion of an upper surface of the first insulating layer (100), and wherein a width of a portion (see fig. 1C), of the first metal layer, adjacent to the upper surface of the first insulating layer is narrower than a width of an upper surface of the first metal layer (150). But, Watanabe et al. does not explicitly teach a second metal layer disposed on the first metal layer. However, Furutani teaches a second metal layer (21p, see figs. 1 and 2I) disposed on the first metal layer (34, see fig. 1). Therefore, At the time of the invention, it would have been obvious before the effective filing date of the claimed invention to a person of ordinary skill in the art to provide a second metal layer disposed on the first metal layer in the device of Watanabe et al. based on the teachings of Furutani in order to improve device reliability and performance at advanced nodes, furthermore, higher conductivity and provide copper fill quality. Pertaining to claim 3, Watanabe et al. discloses, wherein a width of a portion of the second metal layer (21p), adjacent to the upper surface of the first insulating layer (102, see fig. 2I) is narrower than a width of an upper surface of the second metal layer (21p). Pertaining to claim 4, Watanabe et al. discloses, wherein at least a portion of a side surface of the second metal layer (21p) in the protruding portion has an inclined surface (see fig. 2I). Pertaining to claim 5, Watanabe et al. as modified by Furutani further discloses, wherein a side surface of the first metal layer (150 of Watanabe et al.) in the protruding portion has an inclined surface (see fig. 1-5 of Watanabe et al.), and an inclination angle between the inclined surface of the first metal layer (150 of Watanabe et al.) and the upper surface of the first insulating layer (100 of Watanabe et al.) is substantially the same as an inclination angle between an extension surface of the inclined surface included in at least the portion of the side surface of the second metal layer (21p of Furutani) and the upper surface of the first insulating layer (100 of Watanabe et al.). Pertaining to claim 6, Watanabe et al. discloses, wherein the first metal layer (21 of Furutani) comprises substantially the same metal as the second metal layer (34 of Furutani). Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe et al. (US 2012/0138336 A1) in view of Lee et al. (US 2015/0062848 A1). Pertaining to claim 10, Watanabe et al. discloses, a first insulating layer (100) including a groove portion on an upper side (see figs. 1-2); a first wiring layer (150) having an embedded portion embedded in the groove portion (see figs. 1-2) and a protruding portion protruding onto the first insulating layer (100); and a second wiring layer (120) embedded in the first insulating layer (100), and disposed below and spaced apart from the first wiring layer (150). But, Watanabe et al. does not explicitly teach wherein a wiring density of the first wiring layer is greater than a wiring density of the second wiring layer. However, Lee et al. teaches wherein a wiring density of the first wiring layer is greater than a wiring density of the second wiring layer, (Abstract). Therefore, At the time of the invention, it would have been obvious before the effective filing date of the claimed invention to a person of ordinary skill in the art to provide wherein a wiring density of the first wiring layer is greater than a wiring density of the second wiring layer in the device of Watanabe et al. based on the teachings of Lee et al. in order to improve cell packing density and reduced chip area. Pertaining to claim 11, Watanabe et al. discloses, wherein the protruding portion of the first wiring layer has a substantially constant width (see figs. 1-2). Pertaining to claim 12, Watanabe et al. discloses, wherein a width of an upper portion of the embedded portion is substantially the same as a width of a lower portion of the protruding portion (see figs. 1-2). Allowable Subject Matter Claims 7 and 13-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: regarding claim 7, the specific limitations of "wherein the first wiring layer comprises a third metal layer disposed below the first metal layer, and the third metal layer comprises a different metal from the first metal layer," in combination with the remaining elements, are not taught or adequately suggested by the prior art of record. Referring to claim 13, the specific limitations of " wherein the first wiring layer comprises a first metal layer disposed on an inner wall of the groove portion and extending to protrude onto the first insulating layer, a second metal layer disposed on the first metal layer, and a third layer disposed on the second metal layer," in combination with the remaining elements, are not taught or adequately suggested by the prior art of record. Claim 14-16 depend from claim 13 and is therefore allowed for at the same reasons. 9. Claims 17-20 are allowed. 10. The following is a statement of reasons for the indication of allowable subject matter: a protruding portion protruding onto the insulating layer, wherein the wiring layer comprises a first metal layer disposed on an inner wall of the groove portion, a second metal layer disposed on the first metal layer, and a third layer disposed on the second metal layer, each of the first, second, and third metal layer includes a portion disposed in the groove portion and a portion protruding onto the insulating layer, and the second metal layer comprises a different metal than the first metal layer. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ko et al. (2022/0320027 A1) and Kawai et al. (US 2012/0066901 A1). Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDARGIE M AYCHILLHUM whose telephone number is (571)270-1607. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANDARGIE M AYCHILLHUM/Primary Examiner, Art Unit 2848
Read full office action

Prosecution Timeline

May 30, 2024
Application Filed
Mar 06, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
99%
With Interview (+15.0%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 1069 resolved cases by this examiner. Grant probability derived from career allow rate.

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