DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11-13 and 15-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0305381 A1 to Chiang et al. (hereinafter “Chiang”).
Regarding claim 11, Chiang discloses a semiconductor device, comprising:
a substrate (semiconductor device 200 having substrate; Fig. 2; paragraphs [0012]-[0013]);
a lower power line buried in the substrate and extending in a first direction parallel to a bottom surface of the substrate (backside power rail 284 on back side of substrate and extending in direction parallel to bottom surface of substrate 201; Fig. 22B; paragraph [0058]);
a source/drain pattern on the substrate (source/drain features 260 on substrate; Fig. 22B; paragraph [0060]); and
a backside contact structure penetrating the substrate and electrically connecting the lower power line to the source/drain pattern, wherein the backside contact structure comprises a backside via pattern and a backside conductive contact sequentially arranged on the lower power line (backside contact 282 comprising via and conductive fill on rail 284 to electrically connect rail 284 to source/drain features 260; Fig. 22B; paragraphs [0056]-[0058]), and wherein the backside conductive contact comprises a first region having a width in the first direction that increases as a distance from the source/drain pattern increases in a downward direction (topmost portion of contact 282 has width that increases as distance from source/drain features 260 increases; Fig. 21D) and a second region having a width in the first direction that decreases as a distance from the first region increases in a downward direction (part of top half of contact 282 below topmost portion has a width that decreases as distance from topmost portion increases in downward direction; Fig. 21D).
Regarding claim 12, Chiang discloses the semiconductor device of claim 11, wherein a height of the first region is greater than a height of the second region (topmost portion of contact 282 has greatest height; Fig. 21D).
Regarding claim 13, Chiang discloses the semiconductor device of claim 11, wherein a width of the backside via pattern in the first direction increases as a distance from the source/drain pattern increases (width of via increases as distance from source/drain features 260 increases; Fig. 21D).
Regarding claim 15, Chiang discloses the semiconductor device of claim 11, wherein a curvature of a side surface of the second region is larger than a curvature of a side surface of the first region (side surface of contact 282 has greater curvature than top surface; Fig. 21D).
Regarding claim 16, Chiang discloses the semiconductor device of claim 11, wherein the source/drain pattern comprises a pair of source/drain patterns adjacent to each other in the first direction, wherein the backside contact structure is in contact with one of the pair of source/drain patterns, and wherein the semiconductor device further comprises a backside alignment pattern in contact with the other of the pair of source/drain patterns and includes silicon-germanium (SiGe) (two source/drain features 260 laterally adjacent one another, where contact 282 contacts one feature 260 and layer of concave SiGe semiconductor layer 239 contacts another adjacent feature 260; Figs. 10B and 22B; paragraph [0036]).
Regarding claim 17, Chiang discloses the semiconductor device of claim 11, wherein the second region covers a top surface of the backside via pattern (part of top half of contact 282 disposed over top surface of via; Fig. 21D).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 14 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang.
Regarding claim 1, Chiang discloses a semiconductor device, comprising:
a substrate (semiconductor device 200 having substrate; Fig. 2; paragraphs [0012]-[0013]);
a lower power line buried in the substrate and extending in a first direction parallel to a bottom surface of the substrate (backside power rail 284 on back side of substrate and extending in direction parallel to bottom surface of substrate 201; Fig. 22B; paragraph [0058]);
a source/drain pattern on the substrate (source/drain features 260 on substrate; Fig. 22B; paragraph [0060]); and
a backside contact structure provided to penetrate the substrate and electrically connect the lower power line to the source/drain pattern, wherein the backside contact structure includes a backside via pattern and a backside conductive contact sequentially arranged on the lower power line (backside contact 282 comprising via and conductive fill on rail 284 to electrically connect rail 284 to source/drain features 260; Fig. 22B; paragraphs [0056]-[0058]), wherein a side surface of the backside conductive contact is concave in an outward direction from an inner portion of the backside conductive contact toward an outside (contact 282 has concave shape alongside surfaces thereof; Fig. 21D), and wherein a width of the backside conductive contact in the first direction is greater at a first level, such that the width of the backside conductive contact in the first direction increases as a distance from the source/drain pattern increases in a direction toward the first level (width of contact 282 greater at bottom portion than middle portion and the width increases toward top portion away from source/drain features 260; Fig. 21D).
Chiang fails to explicitly disclose a side surface of the backside conductive contact is convex.
However, Chiang discloses the source/drain feature 260 having a side surface with a convex shape (Fig. 21E).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chiang in this manner in order to potentially provide increased effective contact area and volume, and better etch protection and process window during backside processing. Further, this feature is not new in the art as evidenced by US 2022/0359397 A1 to Chang et al. and US 2011/0062564 A1 to Gruenhagen et al. which disclose convex-shaped backside contacts.
Regarding claim 2, Chiang discloses the semiconductor device of claim 1, further comprising a backside barrier pattern between the backside conductive contact and the backside via pattern (contact 282 may comprise a conductive barrier layer around conductive fill to prevent metal diffusion into adjacent dielectric layers; paragraph [0057]).
Regarding claim 3, Chiang discloses the semiconductor device of claim 1, wherein the backside conductive contact and the backside via pattern are connected to each other without any interface therebetween (contact 282 may not comprise a conductive barrier layer; paragraph [0057]).
Regarding claim 4, Chiang discloses the semiconductor device of claim 1, wherein a distance from the first level to an uppermost surface of the backside conductive contact is larger than a distance from the first level to a lowermost surface of the backside conductive contact (bottom portion disposed further away from top surface of contact 282 than bottom surface; Fig. 21D).
Regarding claim 5, Chiang discloses the semiconductor device of claim 1, wherein the backside conductive contact comprises a first region at a level higher than the first level, and a second region at a level lower than the first level, and wherein a width of the second region in the first direction decreases as a distance from the source/drain pattern increases (top portion of contact 282 higher than bottom portion, and bottommost portion lower than bottom portion, and width of bottommost portion decreases as distance from source/drain features 260 increases; Fig. 21D).
Regarding claim 6, Chiang discloses the semiconductor device of claim 5, wherein a height of the first region is larger than a height of the second region (top portion higher than bottom portion; Fig. 21D).
Regarding claim 7, Chiang discloses the semiconductor device of claim 1, wherein a width of the backside via pattern in the first direction increases as a distance from the source/drain pattern increases (width of via increases as distance from source/drain features 260 increases; Fig. 21D).
Regarding claim 8, Chiang discloses the semiconductor device of claim 1, wherein the source/drain pattern comprises a pair of source/drain patterns adjacent to each other in the first direction, wherein the backside contact structure is in contact with one of the pair of source/drain patterns, and wherein the semiconductor device further comprises a backside alignment pattern that is in contact with the other of the pair of source/drain patterns and includes silicon-germanium (SiGe) (two source/drain features 260 laterally adjacent one another, where contact 282 contacts one feature 260 and layer of concave SiGe semiconductor layer 239 contacts another adjacent feature 260; Figs. 10B and 22B; paragraph [0036]).
Regarding claim 9, Chiang discloses the semiconductor device of claim 1, wherein the backside conductive contact has a first side surface arranged on the first level, and a second side surface arranged below the first level, and wherein a curvature of the second side surface is larger than a curvature of the first side surface (top surface of contact 282 is disposed upon bottom portion, and side surface of contact 282 extends below the bottom portion, and side surface of contact 282 has greater curvature than top surface; Fig. 21D).
Regarding claim 10, Chiang discloses the semiconductor device of claim 1, wherein the backside conductive contact covers a top surface of the backside via pattern (conductive fill of contact 282 covers top surface of via; Fig. 21D).
Regarding claim 14, Chiang discloses the semiconductor device of claim 11, wherein a side surface of each of the first and second regions is concave in an outward direction from an inner portion of the backside conductive contact toward an outside (contact 282 has concave shape alongside surfaces thereof; Fig. 21D).
Chiang fails to explicitly disclose a side surface of each of the first and second regions is convex.
However, Chiang discloses the source/drain feature 260 having a side surface with a convex shape (Fig. 21E).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chiang in this manner in order to potentially provide increased effective contact area and volume, and better etch protection and process window during backside processing. Further, this feature is not new in the art as evidenced by US 2022/0359397 A1 to Chang et al. and US 2011/0062564 A1 to Gruenhagen et al. which disclose convex-shaped backside contacts.
Regarding claim 18, Chiang discloses a semiconductor device, comprising:
a substrate (semiconductor device 200 having substrate; Fig. 2; paragraphs [0012]-[0013]);
a lower power line in the substrate and extending parallel to a bottom surface of the substrate (backside power rail 284 on back side of substrate and extending in direction parallel to bottom surface of substrate 201; Fig. 22B; paragraph [0058]);
a source/drain pattern on the substrate (source/drain features 260 on substrate; Fig. 22B; paragraph [0060]);
a channel pattern on the substrate, the channel pattern including a plurality of semiconductor patterns stacked to be spaced apart from each other (semiconductor layers 215 spaced apart from one another and stacked upon substrate; Fig. 21B);
a gate electrode between the plurality of semiconductor patterns (gate electrode layer 350 disposed between layers 215; Fig. 21C); and
a backside contact structure penetrating the substrate and electrically connecting the lower power line to the source/drain pattern, wherein the backside contact structure comprises a backside via pattern and a backside conductive contact sequentially arranged on the lower power line (backside contact 282 comprising via and conductive fill on rail 284 to electrically connect rail 284 to source/drain features 260; Fig. 22B; paragraphs [0056]-[0058]), wherein a side surface of the backside conductive contact is concave in an outward direction from an inner portion of the backside conductive contact toward an outside (contact 282 has concave shape alongside surfaces thereof; Fig. 21D), and wherein a width of the backside conductive contact measured in a first direction parallel to the bottom surface of the substrate is greater at a first level and increases as a distance from the source/drain pattern increases in a direction toward the first level (width of contact 282 greater at bottom portion than middle portion and the width increases toward top portion away from source/drain features 260; Fig. 21D).
Chiang fails to explicitly disclose a side surface of the backside conductive contact is convex.
However, Chiang discloses the source/drain feature 260 having a side surface with a convex shape (Fig. 21E).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chiang in this manner in order to potentially provide increased effective contact area and volume, and better etch protection and process window during backside processing. Further, this feature is not new in the art as evidenced by US 2022/0359397 A1 to Chang et al. and US 2011/0062564 A1 to Gruenhagen et al. which disclose convex-shaped backside contacts.
Regarding claim 19, Chiang discloses the semiconductor device of claim 18, wherein the backside conductive contact comprises a first region at a level higher than the first level, and a second region at a level lower than the first level, and wherein a width of the second region in the first direction decreases as a distance from the source/drain pattern increases (top portion of contact 282 higher than bottom portion, and bottommost portion lower than bottom portion, and width of bottommost portion decreases as distance from source/drain features 260 increases; Fig. 21D).
Regarding claim 20, Chiang discloses the semiconductor device of claim 19, wherein an area of the first region is larger than an area of the second region, when viewed in a sectional view (top portion of contact 282 having larger area in cross-sectional view than bottommost portion of contact 282; Fig. 21D).
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2022/0359397 A1 to Chang et al. and US 2011/0062564 A1 to Gruenhagen et al. each discloses semiconductor devices with backside structures each having convex-shaped backside contact structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights