DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Response to Amendment
The amendment filed March 23, 2026 has been entered. Claims 1-20 remain pending in this application. Claims 1-3, 11, 14-15, and 18 have been amended. No claims have been added. No new matter has been added.
Applicant’s amendments to the Title, Specification, Drawings, and Claims have overcome each and every objection and 112(b) rejection previously set forth in the Non-Final Office Action mailed December 13, 2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 18-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2022/0165347 A1 to Dong Pan (hereafter Pan).
Regarding Amended Independent Claim 18, Pan discloses a method of operating a memory device, comprising:
receiving an active command corresponding to a target memory cell row among a plurality of memory cell rows (Receiving a command corresponding to a target memory row: Pan, ¶[0014]);
receiving a precharge command corresponding to the target memory cell row (Receiving a precharge command: Pan, ¶[0079]);
based on the precharge command,
generating an internal active count update signal (Performing row count update operations upon receiving a precharge command: Pan, ¶[0079])
corresponding to the target memory cell row (Corresponding to the row: Pan, ¶[0079]);
based on the internal active count update signal,
generating a plurality of control signals that update count data with respect to the target memory cell row (Updating the count data with respect to the row: Pan, ¶[0079]); and
based on the precharge command (In response to the precharge command: Pan, ¶[0079]),
performing a precharge operation on the target memory cell row after an active count update time is elapsed (Performing the precharge operation after the expiration of a delay: Pan, ¶[0079])
from a time point when the precharge command is received (Performing the precharge operation after a delay starting from when the precharge command is received: Pan, ¶[0079]).
Regarding Claim 19, Pan discloses the method of claim 18, comprising
performing a read-modify-write (RMW) operation (Reading, updating, and writing a row access count: Pan, ¶[0014]),
wherein the RMW operation
reads out count data corresponding to the target memory cell row during the active count update time (Reading out the number of row accesses performed within a set period of time: Pan, ¶[0014]),
updates the read-out count data (Updating the read count data: Pan, ¶[0014]), and
writes the updated read-out count data in a memory cell array (Writing back the updated count data: Pan, ¶[0014]).
Regarding Claim 20, Pan discloses the method of claim 18, comprising
performing a refresh operation on a memory cell row (Performing a refresh operation on a victim row: Pan, ¶[0012])
adjacent to the target memory cell row (A victim row being one adjacent to a frequently accessed row: Pan, ¶[0064])
based on a value of the count data with respect to the target memory cell row being equal to or greater than a predetermined value (The refresh operation taking place in response to a number of access of a row reaches a predetermined threshold: Pan, ¶[0012]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 7-9, and 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0165347 A1 to Dong Pan (hereafter Pan) in view of EP 4,123,650 A1 to Sungyong Cho, et al. (hereafter Cho).
Regarding Amended Independent Claim 1, Pan discloses a memory device comprising:
a memory cell array (A memory cell array: Pan, ¶[0010]) comprising a plurality of memory cell rows (A plurality of memory cell word lines: Pan, ¶[0010]),
the memory cell array configured to
store count data for a number of accesses (Counting row access: Pan, ¶[0014])
to each memory cell row of the plurality of memory cell rows (Counting accesses to each word line: Pan, ¶[0014]);
a row hammer management circuit (A refresh control circuit 316 and a Count Control Circuit 328: Pan, Figure 3) configured to:
perform a read-modify-write (RMW) (The Count Control Circuit performing a read adjust write operation: Pan, ¶[0014]) operation
that reads out count data (The Count Control Circuit reading out the access count data: Pan, ¶[0014])
corresponding to a target memory cell row among the plurality of memory cell rows (The access count data corresponding to a particular word line: Pan, ¶[0014]),
update the read-out count data (Count Control Circuit 328 adjusting the count data: Pan, ¶[0014), and
write the updated read-out count data in the memory cell array (Writing the access count data back to the word line: Pan, ¶[0014]); and
an RMW driver configured to generate a plurality of RMW control signals (A circuit configured to control row count operations: Pan, Figure 3),
wherein the RMW driver is configured to generate the plurality of RMW control signals
based on a precharge command (Waiting to write the access count back to the wordline until receiving a Precharge command: Pan, ¶[0079]), and
wherein a precharge operation on the target memory cell row
is performed after a predetermined time is elapsed (A PreCharge delay: Pan, ¶[0079])
from a time point when the precharge command is received by the RMW driver (The delay implemented between receiving the precharge command and performing the precharge operation: Pan, ¶[0079]).
Pan discloses performing a write operation upon receipt of a precharge command, but omits performing a write operation in response to a precharge command and only implies performing an update (Pan, ¶[0079]). Cho, however, explicitly discloses performing a full read-update-write sequence in response to receiving a precharge instruction (Cho, ¶[0021]). Cho teaches performing this operation in response to a precharge command ensures the precharge operation is included in the command (Cho, ¶[0021]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to use the precharge signal to trigger an update operation, as in Cho, in conjunction with the update methodology of Pan, with a reasonable expectation of success. Both inventions are well known in the field of row hammer mitigation and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Claim 2, Pan discloses the memory device of claim 1, wherein
the RMW operation with respect to the target memory cell row (Waiting to write the access count back to the wordline until receiving a Precharge command: Pan, ¶[0079]) and
the precharge operation with respect to the target memory cell row are performed based on the precharge command (Performing row count update operations upon receiving a precharge command: Pan, ¶[0079]).
Regarding Amended Claim 3, Pan discloses the memory device of claim 2, wherein
the RMW operation with respect to the target memory cell row is performed (Updating count values and writing them to the wordline: Pan, ¶[0079])
based on the precharge command (Based on receiving the precharge command: Pan, ¶[0079])
during an active count update time (Performing the count update between receiving the precharge command and the expiration of a delay: Pan, ¶[0079]), and
the target memory cell row is precharged based on the precharge command (Precharging the wordline: Pan, ¶[0079])
after the active count update time is elapsed (Providing time between after receiving the precharge command: Pan, ¶[0079])
from the time point where the precharge command is received (Precharging the wordline after a delay: Pan, ¶[0079]).
Regarding Claim 7, Pan and Cho disclose the memory device of claim 1, wherein the RMW driver comprises:
an internal active count update signal generator (A count control circuit 328: Pan, Figure 3) configured to
based on the precharge command (In response to a precharge command: Cho, ¶[0021]),
generate an internal active count update signal (Generate a Read-Modify-Write operation: Cho, ¶[0021])
with respect to a bank corresponding to the precharge command (The circuitry associated with a particular bank: Cho, Figure 3); and
an RMW control circuit (A refresh control circuit 316 and a Count Control Circuit 328: Pan, Figure 3) configured to
based on the internal active count update signal (Generate a Read-Modify-Write operation: Cho, ¶[0021]), generate an RMW core signal group (Generating a signal to perform a RMW operation: Cho, ¶[0021])
that controls an RMW operation of the bank corresponding to the precharge command (Circuitry associated with a particular bank: Pan, ¶[0054]).
Regarding Claim 8, Pan discloses the memory device of claim 7, wherein the internal active count update signal generator is configured to
maintain a level of the internal active count update signal at a high level during the predetermined time (Disclosing incrementing the access count only for operations performed during a certain interval of time: Pan, ¶[0014]; Tracking the lapse of time via some sort of signal is inherent in tracking a time interval).
Regarding Claim 9, Pan discloses the memory device of claim 8, wherein the RMW control circuit comprises:
an oscillator configured to generate an oscillation signal (Count Control Circuit 128 including a timer in the form of a clock: Pan, ¶[0030])
during the high level of the internal active count update signal (The row count window tracked by clock cycles: Pan, ¶¶[0014] and [0030]); and
a core signal generator configured to generate,
based on a rising edge or a falling edge of the oscillation signal (The Count Control Circuit updating the count based on the clock signal: Pan, ¶[0030]),
the RMW core signal group that controls the RMW operation of the bank corresponding to the precharge command (Updating the access count in accordance with the precharge signal: Pan, ¶[0031]).
Regarding Amended Claim 11, Pan discloses the memory device of claim 1, comprising
a control logic circuit configured to generate,
based on the precharge command (In response to a precharge signal: Pan, ¶[0055]),
an internal precharge signal that precharges the target memory cell row (The given bank being precharged in response to a precharge signal: Pan, ¶[0055])
after the predetermined time is elapsed from the time point where the precharge command is received (Precharging the designated lines after a predetermined delay following the receipt of a precharge command: Pan, ¶[0079]).
Regarding Claim 12, Pan discloses the memory device of claim 1, wherein the row hammer management circuit is configured
to perform a refresh operation on a memory cell row (Performing a refresh operation on a victim row: Pan, ¶[0012])
adjacent to the target memory cell row (A victim row being one adjacent to a frequently accessed row: Pan, ¶[0064])
based on a value of the updated read-out count data being equal to or greater than a predetermined value (The refresh operation taking place in response to a number of access of a row reaches a predetermined threshold: Pan, ¶[0012]).
Regarding Claim 13, Pan discloses the memory device of claim 1, comprising
an ECC engine configured to perform an error correction operation on the read-out count data (Using ECC to correct errors in the read count: Pan, ¶[0077]).
Claim(s) 4-6 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0165347 A1 to Dong Pan (hereafter Pan) and EP 4,123,650 A1 to Sungyong Cho, et al. (hereafter Cho) in view of US 2022/0121398 A1 to Bill Nale, et al. (hereafter Nale).
Regarding Claim 4, Pan discloses the memory device of claim 1, wherein
the memory cell array comprises a first bank and a second bank comprising the plurality of memory cell rows (The memory array divided into separate banks of memory: Pan, ¶[0019]), and
wherein the RMW driver is configured to:
receive a first precharge command corresponding to the first bank (Receiving a precharge command at the bank level: Pan, ¶[0079]),
receive a second precharge command corresponding to the second bank (Receiving a precharge command at the bank level: Pan, ¶[0079]; Note, While Pan only discloses the precharge operation at a single bank level, it discloses the circuitry controlling the count operations being repeated for each bank: Pan, ¶[0054]),
generate a first internal active count update signal corresponding to the first bank based on the first precharge command (Updating count values and writing them to a wordline in response to receiving a precharge command: Pan, ¶[0079]), and
generate a second internal active count update signal corresponding to the second bank based on the second precharge command (Updating the wordline access data on receipt of a precharge command: Pan, ¶[0079]); Note, While Pan only discloses the precharge operation at a single bank level, it discloses the circuitry controlling the count operations being repeated for each bank: Pan, ¶[0054]).
Pan discloses separate circuitry being provided each bank (Pan, ¶[0054]). It is implied, but not explicitly stated, that separate circuitry is provided to allow for parallel operation across different banks of memory. Nale, however, explicitly discloses providing parallel access to different banks simultaneously (Nale, ¶[0004). Nale teaches this parallel operation can offset the performance impact of the read-modify-write operation (Nale, ¶[0004]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to operate the separate memory banks of Pan independently as in Nale, with a reasonable expectation of success. Both inventions are well known in the field of bank level operations in row hammer mitigation strategies and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 5, Pan and Nale disclose the memory device of claim 4, wherein
a section in which the first internal active count update signal corresponding to the first bank is activated (Activating the internal active count update in a bank: Pan, ¶[0014])
overlaps (Disclosing parallel operations taking place in multiple banks simultaneously: Nale, ¶[0004])
a section in which the second internal active count update signal corresponding to the second bank is activated (Activating the internal active count update in a bank: Pan, ¶[0014]).
Regarding Claim 6, Pan and Nale disclose the memory device of claim 4, wherein the RMW driver is configured to:
generate a first RMW core signal group that controls an RMW operation of the first bank (Controlling the RMW signal in a bank: Pan, ¶[0014])
based on the first internal active count update signal (Based on a signal: Pan, ¶[0031]), and
generate a second RMW core signal group (Disclosing parallel operations taking place in multiple banks simultaneously: Nale, ¶[0004])
that controls an RMW operation of the second bank (Controlling the RMW signal in a bank: Pan, ¶[0014])
based on the second internal active count update signal (Based on a signal: Pan, ¶[0031]).
Regarding Amended Independent Claim 14, Pan discloses a memory device comprising:
a memory cell array (A memory cell array: Pan, ¶[0010]) comprising
a first bank and a second bank (The memory array divided into separate banks of memory: Pan, ¶[0019])
comprising a plurality of memory cell rows (A plurality of memory cell word lines: Pan, ¶[0010]);
a row hammer management circuit (A refresh control circuit 316 and a Count Control Circuit 328: Pan, Figure 3) configured
to perform a first read-modify-write (RMW) operation (The Count Control Circuit performing a read adjust write operation: Pan, ¶[0014])
with respect to the first bank (Disclosing circuitry controlling the count operations being repeated for each bank: Pan, ¶[0054]) and
a second RMW operation (The Count Control Circuit performing a read adjust write operation: Pan for a bank, ¶[0014]); and
an RMW driver configured to
generate a first RMW core signal group (A circuit configured to control row count operations: Pan, Figure 3) and
a second RMW core signal group (A circuit configured to control row count operations: Pan, Figure 3),
the first RMW core signal group controlling the first RMW operation with respect to the first bank (A circuit configured to control row count operations: Pan, Figure 3) and
the second RMW core signal group controlling the second RMW operation with respect to the second bank (A circuit configured to control row count operations: Pan, Figure 3), wherein
the first RMW core signal group is generated based on a first precharge command with respect to the first bank (Waiting to write the access count back to the wordline until receiving a Precharge command: Pan, ¶[0079]) and
the second RMW core signal group is generated based on a second precharge command with respect to the second bank (Waiting to write the access count back to the wordline until receiving a Precharge command: Pan, ¶[0079]),
a first precharge operation
corresponding to the first precharge command (In response to a precharge command: Pan, ¶[0079])
is performed after a time delay (A Precharge delay: Pan, ¶[0079])
by an active count update time (Disclosing incrementing the access count only for operations performed during a certain interval of time: Pan, ¶[0014]) from a time point where the first precharge command is received (The delay implemented between receiving the precharge command and performing the precharge operation: Pan, ¶[0079]), and
a second precharge operation
corresponding to the second precharge command (In response to a precharge command: Pan, ¶[0079])
is performed after a time delay (A Precharge delay: Pan, ¶[0079])
by the active count update time (Disclosing incrementing the access count only for operations performed during a certain interval of time: Pan, ¶[0014]) from a time point where the second precharge command is received (The delay implemented between receiving the precharge command and performing the precharge operation: Pan, ¶[0079]).
Pan discloses performing a write operation upon receipt of a precharge command, but omits performing a write operation in response to a precharge command and only implies performing an update (Pan, ¶[0079]). Cho, however, explicitly discloses performing a full read-update-write sequence in response to receiving a precharge instruction (Cho, ¶[0021]). Cho teaches performing this operation in response to a precharge command ensures the precharge operation is included in the command (Cho, ¶[0021]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to use the precharge signal to trigger an update operation, as in Cho, in conjunction with the update methodology of Pan, with a reasonable expectation of success. Both inventions are well known in the field of row hammer mitigation and the combination of known inventions with predictable results is obvious and not patentable.
Pan discloses separate circuitry being provided each bank (Pan, ¶[0054]). It is implied, but not explicitly stated, that separate circuitry is provided to allow for parallel operation across different banks of memory. Nale, however, explicitly discloses providing parallel access to different banks simultaneously (Nale, ¶[0004). Nale teaches this parallel operation can offset the performance impact of the read-modify-write operation (Nale, ¶[0004]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to operate the separate memory banks of Pan independently as in Nale, with a reasonable expectation of success. Both inventions are well known in the field of bank level operations in row hammer mitigation strategies and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Claim 15, Pan discloses the memory device of claim 14, comprising
a control logic circuit configured to
generate a first internal precharge signal and a second internal precharge signal (Precharging the wordline in response to a signal: Pan, ¶[0079])
based on the first precharge command and the second precharge command, respectively (Updating count values and writing them to a wordline in response to receiving a precharge command: Pan, ¶[0079]),
wherein the first internal precharge signal is generated after the time delay (A Precharge delay: Pan, ¶[0079]) by the active count update time from the time point where the first precharge command is received (The delay implemented between receiving the precharge command and performing the precharge operation: Pan, ¶[0079]), and
the second internal precharge signal is generated after the time delay (A Precharge delay: Pan, ¶[0079]) by the active count update time from the time point where the second precharge command is received (The delay implemented between receiving the precharge command and performing the precharge operation: Pan, ¶[0079]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0165347 A1 to Dong Pan (hereafter Pan) and EP 4,123,650 A1 to Sungyong Cho, et al. (hereafter Cho) in view of US 9,362,006 B2 to Yohan U. Frans, et al. (hereafter Frans).
Regarding Claim 10, Pan discloses the memory device of claim 9, but fails to disclose the further limitations of Claim 10. Frans, however, discloses a memory device, wherein
the oscillation signal has a frequency that changes (A changing oscillation circuit: Frans, col.1:64-66)
as an operation frequency of the memory device changes (The clock signal changing in response to broader device circumstances: Frans, col.2:4-10).
Frans teaches tracking clock signal frequency variations can help account for timing drift due to external factors such as due to temperature or device state (Frans, col.1:21-37). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the clock variation tracking of Frans with the timing circuit of Pan, with a reasonable expectation of success. Both inventions are well known in the field of time interval tracking in memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0165347 A1 to Dong Pan (hereafter Pan), EP 4,123,650 A1 to Sungyong Cho, et al. (hereafter Cho), and US 2022/0121398 A1 to Bill Nale, et al. (hereafter Nale) in view of US 2014/0059287 A1 to Kuljit Bains, et al. (hereafter Bains).
Regarding Claim 16, Pan discloses the memory device of claim 15, wherein
the RMW driver comprises an internal active count update signal generator (A count control circuit 328: Pan, Figure 3) configured to:
generate
a first internal active count update signal corresponding to the first bank (Generate a Read-Modify-Write operation: Cho, ¶[0021]) and
a second internal active count update signal corresponding to the second bank (Generate a Read-Modify-Write operation: Cho, ¶[0021]),
Pan does not expressly disclose transitioning a level of the internal active count update signal from a low level to a high level based on the precharge command for either the first or second instance, nor transitioning the level of the internal active count update signal from the high level to the low level for either the first or second instance. Bains, however, discloses a memory device as in Claim 15, configured to:
transition a level of the first internal active count update signal from a low level to a high level based on the first precharge command (Transitioning from a low to high signal based on a command: Bains, Figure 5),
transition the level of the first internal active count update signal from the high level to the low level based on the first internal precharge signal (Transitioning from a low to high signal based on a command: Bains, Figure 5),
transition a level of the second internal active count update signal from the low level to the high level (Transitioning from a high level to a low level: Bains, Figure 5) based on the second precharge command (In response to a second command: Bains, ¶[0058]), and
transition the level of the second internal active count update signal from the high level to the low level (Transitioning from a high level to a low level: Bains, Figure 5) based on the second internal precharge signal (In response to a second command: Bains, ¶[0058]).
Bains teaching switching between data states in response to command signals allows a single bit to track multiple command signals (Bains, ¶[0061]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to use the combine signal method of Bains to implement the precharge signals of Pan, with a reasonable expectation of success. Both inventions are well known in the field of row hammer mitigation methods and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 17, Pan discloses the memory device of claim 16, wherein
the RMW driver comprises an RMW control circuit configured to:
generate the first RMW core signal group corresponding to the first bank based on the first internal active count update signal (Disclosing incrementing the access count only for operations performed during a certain interval of time: Pan, ¶[0014]; Tracking the lapse of time via some sort of signal is inherent in tracking a time interval), and
generate the second RMW core signal group corresponding to the second bank based on the second internal active count update signal (Disclosing incrementing the access count only for operations performed during a certain interval of time: Pan, ¶[0014]; Tracking the lapse of time via some sort of signal is inherent in tracking a time interval), and
wherein the RMW control circuit comprises:
an oscillator configured to:
generate a first oscillation signal (Count Control Circuit 128 including a timer in the form of a clock: Pan, ¶[0030]) during a time in which the first internal active count update signal is maintained at the high level (The row count window tracked by clock cycles: Pan, ¶¶[0014] and [0030]), and
generate a second oscillation signal (Count Control Circuit 128 including a timer in the form of a clock: Pan, ¶[0030]) during a time in which the second internal active count update signal is maintained at the high level (The row count window tracked by clock cycles: Pan, ¶¶[0014] and [0030]); and
a core signal generator configured to:
generate the first RMW core signal group based on a rising edge or a falling edge of the first oscillation signal (The Count Control Circuit updating the count based on the clock signal: Pan, ¶[0030]), and
generate the second RMW core signal group based on a rising edge or a falling edge of the second oscillation signal (The Count Control Circuit updating the count based on the clock signal: Pan, ¶[0030]).
Response to Arguments
Applicant's arguments filed March 23, 2026 have been fully considered but they are not persuasive.
Applicant argues Pan fails to teach the amended elements of independent claims 1, 14, and 18, and relevant limitations of the remaining dependent claims. Specifically, Applicant argues Pan fails to disclose performing a precharge operation at all, much less performing the precharge operation after a predetermined time is elapsed from a time point when the precharge command is received by the RMW driver (Applicant Argument/Remarks, page 10, ¶2). In this same paragraph, however, Applicant admits Pan teaches waiting for a precharge command and a time needed for performing a writing operation after the precharge command (Applicant Argument/Remarks, page 10, ¶2). Taken at face value, this argument therefore implies Pan teaches the driver receiving a Precharge command, not performing a precharge operation, but nonetheless waiting for an undisclosed period before performing an unrelated write operation. This interpretation of the text is not persuasive.
In Paragraph 79, Pan state in reference to one embodiment of updating the disclosed access counters as, “However, waiting for the precharge command may increase the row precharge time (tRP) of the memory because time must be provided after the precharge command for writing the updated count values back to the count value memory cells.” In other embodiments, updating the count value takes place independently of the precharge command (See, for instance, Pan, ¶[0075] stating, “In embodiments where the updated count is written back to the count value memory cells of the word line without regard to the precharge command…”).
Paragraph 79, in contrast, describes an operation wherein the updated count is written back to the count value memory cells as part of the precharge command. Given this context, the above sentence discloses a clear series of events: Receiving a precharge command, delaying to allow writing the the updated count to the count value memory cells, and finally performing the precharge step inherent in any precharge operation. The related discussion that this order of operations necessarily increases the length of time required to perform a precharge operation is merely an acknowledgement of an inherent reality, introducing a delay into any operation will increase the duration of that operation.
Therefore, Applicant’s response is unpersuasive. Applicant's response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2017/0271026 A1 to Min Su Park: Disclosing a read control circuit configured to refresh adjacent word lines based on the active count of the word line.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER LANE REECE whose telephone number is (571)272-0288. The examiner can normally be reached Monday - Friday 7:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER LANE REECE/ Examiner, Art Unit 2824
/DOUGLAS KING/ Primary Examiner, Art Unit 2824
Prosecution Insights