DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-7, 9, & 14-22 are rejected under 35 U.S.C. 102(a)(1) & (a)(2) as being anticipated by Sasaki et al (U.S. PGPub # 2020/0241582).
Regarding Independent claim 1, Sasaki teaches:
A temperature adjusting system comprising:
a temperature adjuster that adjusts a temperature of a device under test (DUT) (Fig. 1 Element 70. See paragraph 0038.);
a first acquirer that acquires a first digital signal (Fig. 1 Element 17. See paragraphs 0030-0032 & 0036-0037.) and outputs a second digital signal (Fig. 1 Element 17. See paragraphs 0030-0032 & 0036-0037.), wherein the first digital signal is output from a first temperature detecting circuit (Fig. 1 Elements 92 & 12.) in the DUT and indicates an internal temperature of the DUT (Fig. 1 Element 17. See paragraphs 0030-0032 & 0036-0037.); and
a controller that controls the temperature adjuster using the second digital signal (Fig. 1 Element 87. See paragraphs 0039, 0043, 0047-0049, 0073, & elsewhere.).
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Regarding claim 2, Sasaki teaches all elements of claim 1, upon which this claim depends.
Sasaki teaches the first acquirer generates the second digital signal using the first digital signal (Fig. 1 Element 17. See paragraphs 0030-0032 & 0036-0037.).
Regarding claim 3, Sasaki teaches all elements of claim 1, upon which this claim depends.
Sasaki teaches the controller: sets a target temperature using the second digital signal, and controls the temperature adjuster based on the target temperature (Fig. 1 Element 87. See paragraph 0052.).
Regarding claim 6, Sasaki teaches all elements of claim 3 upon which this claim depends.
Sasaki teaches a second acquirer that acquires a current temperature of the DUT (Fig. 1 Elements 82, 83, 84, & 89. See associated text.), wherein the controller controls the temperature adjuster based on the target temperature and the acquired current temperature (Fig. 1 Element 87. See paragraphs 0039, 0043, 0047-0049, 0073, & elsewhere.).
Regarding claim 7, Sasaki teaches all elements of claim 1, upon which this claim depends.
Sasaki teaches a second acquirer that acquires a current temperature of the DUT (Fig. 1 Elements 82, 83, 84, & 89. See associated text.), wherein the controller: corrects the current temperature using the second digital signal (Fig. 1 Element 87. See paragraphs 0039, 0043, 0047-0049, 0073, & elsewhere.), and controls the temperature adjuster based on the corrected current temperature (Fig. 1 Element 87. See paragraphs 0039, 0043, 0047-0049, 0073, & elsewhere.).
Regarding claim 9, Sasaki teaches all elements of claim 1, upon which this claim depends.
Sasaki teaches the first acquirer acquires the first digital signal using test instructions that perform a test of the DUT (Fig. 1 Element 17. See paragraphs 0030-0032 & 0036-0037.).
Regarding Independent claim 14, Sasaki teaches:
A temperature adjusting system comprising:
a temperature adjuster that adjusts a temperature of a device under test (DUT) (Fig. 1 Element 70. See paragraph 0038.);
a first acquirer that acquires an internal temperature of the DUT and outputs a first signal (Fig. 1 Element 17. See paragraphs 0030-0032 & 0036-0037.);
a second acquirer that acquires a current temperature of the DUT and outputs a second signal (Fig. 1 Element 16. See paragraphs 0030-0032 & 0036-0037.); and
a controller that controls the temperature adjuster using the first signal and the second signal (Fig. 1 Element 87. See paragraphs 0039, 0043, 0047-0049, 0073, & elsewhere.).
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Regarding claim 15, Sasaki teaches all elements of claim 14, upon which this claim depends.
Sasaki teaches the first acquirer acquires a digital signal output from a first temperature detecting circuit in the DUT and indicates the internal temperature of the DUT (Fig. 1 Element 17. See paragraphs 0030-0032 & 0036-0037.), and the second acquirer acquires an analog signal output from a second temperature detecting circuit in the DUT and indicates the current temperature of the DUT (Fig. 1 Elements 82, 83, 84, & 89. See associated text.).
Regarding Independent claim 16, Sasaki teaches:
A controller that controls a temperature adjuster that adjusts a temperature of a device under test (DUT), wherein
a first digital signal is output from a temperature detecting circuit in the DUT and indicates an internal temperature of the DUT (Fig. 1 Elements 92 & 12. See paragraphs 0030-0032 & 0036-0037.),
a second digital signal output from an acquirer that acquires the first digital signal (Fig. 1 Element 17. See paragraphs 0030-0032 & 0036-0037.), and
the controller controls the temperature adjuster using the second digital signal (Fig. 1 Element 87. See paragraphs 0039, 0043, 0047-0049, 0073, & elsewhere.).
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Regarding claim 17, Sasaki teaches all elements of claim 14, upon which this claim depends.
Sasaki teaches an electronic device handling apparatus that handles the DUT or a carrier holding the DUT and presses the DUT or the carrier to a socket (Fig. 1 Element 17. See paragraphs 0030-0032 & 0036-0037.), the electronic device handling apparatus comprising: the temperature adjuster; and the controller according to claim 16 (Fig. 1 Element 17. See paragraphs 0030-0032 & 0036-0037.).
Regarding Independent claim 18, Sasaki teaches:
A tester that tests either a device under test (DUT) electrically connected to a socket or the DUT held in a carrier electrically connected to the socket, the tester comprising:
an acquirer that acquires a first digital signal and outputs a second digital signal (Fig. 1 Element 17. See paragraphs 0030-0032 & 0036-0037.), wherein
the first digital signal is output from a temperature detecting circuit in the DUT and indicating an internal temperature of the DUT (Fig. 1 Elements 92 & 12. See paragraphs 0030-0032 & 0036-0037.).
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Regarding claim 19, Sasaki teaches all elements of claim 1, upon which this claim depends.
Sasaki teaches an electronic device testing apparatus that tests the DUT, comprising: the temperature adjusting system according to claim 1 (See Fig. 1and associated text.).
Regarding claim 20, Sasaki teaches all elements of claim 1, upon which this claim depends.
Sasaki teaches an electronic device testing apparatus that tests the DUT, comprising: the temperature adjusting system according to claim 14 (See Fig. 1and associated text.).
Regarding claim 21 Sasaki teaches all elements of claim 16, upon which this claim depends.
Sasaki teaches an electronic device testing apparatus that tests the DUT (Fig. 1 Element 1. See paragraph 0038.), comprising: the temperature adjuster (Fig. 1 Element 70. See paragraph 0038.); the controller according to claim 16 (Fig. 1 Element 87. See paragraphs 0039, 0043, 0047-0049, 0073, & elsewhere.); and a tester (Fig. 1 Element 10. See paragraphs 0026-0030, 0038, & 0044.), comprising the acquirer (Fig. 1 Element 17. See paragraphs 0030-0032 & 0036-0037.), that tests either the DUT electrically connected to a socket or the DUT held in a carrier electrically connected to the socket (Fig. 1 Elements 20-21. See paragraphs 0029 & 0095.).
Regarding claim 22, Sasaki teaches all elements of claim 17, upon which this claim depends.
Sasaki teaches an electronic device testing apparatus that tests the DUT (Fig. 1 Element 1. See paragraph 0038.), comprising: the electronic device handling apparatus according to claim 17 (Fig. 1 Element 17. See paragraphs 0030-0032 & 0036-0037.), the electronic device handling apparatus comprising: the temperature adjuster; and the controller according to claim 16 (Fig. 1 Element 17. See paragraphs 0030-0032 & 0036-0037.); and a tester (Fig. 1 Element 10. See paragraphs 0026-0030, 0038, & 0044.), comprising the acquirer (Fig. 1 Element 17. See paragraphs 0030-0032 & 0036-0037.), that tests either the DUT electrically connected to the socket or the DUT held in the carrier electrically connected to the socket (Fig. 1 Elements 20-21. See paragraphs 0029 & 0095.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Sasaki et al (U.S. PGPub # 2020/0241582) in view of Cao et al (U.S. PGPub # 2019/0360869).
Regarding claim 10, Sasaki teaches all elements of claim 1, upon which this claim depends.
Sasaki does not explicitly teach the first acquirer executes normalization processing on the first digital signal.
Cao teaches the first acquirer executes normalization processing on the first digital signal (See paragraph 0042.).
It would have been obvious to one of ordinary skill in the art before the effective time of filing to apply the teachings of Cao to the teachings of Sasaki such that the first acquirer executes normalization processing on the first digital signal “so as to standardize and calibrate the temperature sensor.” See paragraph 0042 of Cao.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Sasaki et al (U.S. PGPub # 2020/0241582) in view Agawa (U.S. PGPub # 2013/0100984)
Regarding claim 11, Sasaki teaches all elements of claim 1, upon which this claim depends.
Sasaki teaches the first acquirer executes averaging processing on the first digital signal.
Agawa teaches the first acquirer executes averaging processing on the first digital signal (See paragraphs 0046-0048.).
It would have been obvious to one of ordinary skill in the art before the effective time of filing to apply the teachings of Agawa to the teachings of Sasaki such that the first acquirer executes averaging processing on the first digital signal because this allows one to reduce noise “with respect to the digital signal corresponding to the intensity Ist and the digital signal corresponding to the intensity Ias.” See paragraph 0048 of Agawa.
Allowable Subject Matter
Claims 4-5, 8, & 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art listed does not anticipate alone or combine in an obvious manner to teach the invention claimed by applicant.
Regarding claim 4, Sasaki teaches all elements of claim 3, upon which this claim depends.
Sasaki teaches the controller: sets a reference value, and corrects the reference value using the second digital signal to set the target temperature.
Regarding claim 5,
The temperature adjusting system according to claim 4, wherein the controller: calculates a difference between the reference value and the second digital signal, adjusts the difference, and adds the adjusted difference to the reference value.
Regarding claim 8, Sasaki teaches all elements of claim 1, upon which this claim depends.
Sasaki teaches the second digital signal is irregularly output from the first acquirer to the controller, and the controller converts the second digital signal from an irregular signal to a regular signal.
Regarding claim 12,
The temperature adjusting system according to claim 1, wherein the first acquirer: executes normalization processing on the first digital signal, executes averaging processing on the first digital signal, and enables or disables either the normalization processing or the averaging processing.
Regarding claim 13,
The temperature adjusting system according to claim 1, wherein the first temperature detecting circuit: comprises: a measuring unit that measures the internal temperature of the DUT; and a calibrating unit that calibrates a measurement result of the measuring unit, and outputs the calibrated measurement result as the first digital signal to the first acquirer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art listed but not cited represents the previous state of the art and analogous art that teaches some of the limitations claimed by applicant.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER P MCANDREW whose telephone number is (469)295-9025. The examiner can normally be reached Monday-Thursday 6-4:30.
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/CHRISTOPHER P MCANDREW/Primary Examiner, Art Unit 2858