DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The allowable content as in office action 11/26/2025, has been prior-art-searched/reconsidered, and is not allowable in view of newly found prior art. This office action is being used to replace the office actin dated 11/26/2025 as a Non-Final office action.
Claims 1, 4-5, 10, 13, 18 and 21-34 are pending.
Allowable Subject Matter
Claim 22-23, 24-25, 27, 28, 29, 32-33, 34 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 30 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 30 recites the limitation "the repeating pattern". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 10, 18 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over YUN (PGPUB 20170069358), hereinafter as Yun, in view of Lee (PGPUB 20150003151), hereinafter as Lee.
Regarding claim 1, Yun teaches a memory system comprising:
a memory component comprising a number of bit lines (Fig 1), a plurality of word lines (Fig 1), and a number of sense amplifiers (Fig 1, sense amplifier 110, there are other SA and BLs not shown but are obvious present) equal to the number of bit lines (Fig 1, each BL has a SA 110); and a processing device programmed to perform operations comprising:
setting data values in the number of sense amplifiers (Fig 2, S205); and
using the sense amplifiers, writing the data values to memory cells corresponding to the plurality of word lines (Fig 2, S207),
but not expressly multiple word lines are programmed simultaneously,
Lee teaches multiple word lines are programmed simultaneously ((0385-0386]);
Since Lee and Yun are both from the same field of semiconductor memory device, the purpose disclosed by Lee would have been recognized in the pertinent art of Yun.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to program multiple word lines at the same time as in Lee into the device of Yun for the purpose of managing speeding up the writing data into the memory device.
Regarding claim 10, Yun teaches a method comprising:
setting data values in a number of sense amplifiers of a memory component (Fig 1), the number of sense amplifiers equal to a number of bit lines of a word line of the memory component (Fig 1, and reasoning as that used in rejection of claim 1); and
using the sense amplifiers, writing the data values to memory cells corresponding to a plurality of word lines of the memory component (Fig 2),
but not expressly multiple word lines are programmed simultaneously,
Lee teaches multiple word lines are programmed simultaneously ((0385-0386]);
The reason for combining the references used in rejection of claim 1 applies.
Regarding claim 18, Yun teaches a non-transitory machine-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
setting data values in a number of sense amplifiers of a memory component, the number of sense amplifiers equal to a number of bit lines of a word line of the memory component; and
using the sense amplifiers, writing the data values to memory cells corresponding to a plurality of word lines of the memory component (argument used in rejection of claim 1 applies);
but not expressly multiple word lines are programmed simultaneously,
Lee teaches multiple word lines are programmed simultaneously ((0385-0386]);
The reason for combining the references used in rejection of claim 1 applies.
Regarding claim 26, Yun teaches the operations are performed in response to receiving a single command to write the data values to the plurality of word lines (Fig 2).
Claim(s) 4 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun and Lee, in view of Vogelsang et al. (PGPUB 20150234707), hereinafter as Vogelsang.
Regarding claim 4, Yun and Lee teach a memory system as in rejection of claim 1,
But not expressly the number of bit lines comprise a first number of data bit lines and a second number of error correction code (ECC) bit lines.
Vogelsang teaches the number of bit lines comprise a first number of data bit lines and a second number of error correction code (ECC) bit lines (Fig 1B).
Since Vogelsang and Yun are both from the same field of semiconductor memory device, the purpose disclosed by Vogelsang would have been recognized in the pertinent art of Yun.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use ECC bit line as in Vogelsang into the device of Yun for the purpose of managing error corrections of the memory device.
Regarding claim 13, argument used in rejection of claim 4 applies.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun and Lee, in view of Fujino (PGPUB20030123317), hereinafter as Fujino.
Regarding claim 5, Yun and Lee teach a memory system as in rejection of claim 1,
But not expressly a first row of sense amplifiers that receives data from odd-numbered bit lines in a portion of the memory component; and a second row of sense amplifiers that receives data from even-numbered bit lines in the portion of the memory component.
Fujino teaches a first row of sense amplifiers that receives data from odd-numbered bit lines in a portion of the memory component; and a second row of sense amplifiers that receives data from even-numbered bit lines in the portion of the memory component (Fig 4).
Since Fujino and Yun are both from the same field of semiconductor memory device, the purpose disclosed by Fujino would have been recognized in the pertinent art of Yun.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use the layout as in Fujino into the device of Yun for the purpose of managing physical layout of the memory device.
Claim(s) 21 and 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun and Lee, in view of Kim et al. (PGPUB 20180204620), hereinafter as Kim.
Regarding claim 21, Yun and Lee teach a memory system as in rejection of claim 1,
But not expressly prior to simultaneously activating the plurality of word lines, pre-charging the plurality of word lines simultaneously;
Kim teaches prior to simultaneously activating the plurality of word lines, pre-charging the plurality of word lines simultaneously ([0106]).
Since Kim and Yun are both from the same field of semiconductor memory device, the purpose disclosed by Kim would have been recognized in the pertinent art of Yun.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to precharge the word line as in Kim into the device of Yun for the purpose of managing writing operation of the memory device.
Regarding claim 31, argument used in rejection of claim 21 applies.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MIN HUANG/Primary Examiner, Art Unit 2827