Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/30/2024 has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following features must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 11: wherein the base structure further comprises an interposer substrate comprising an internal wiring layer connecting the lower connection pad to the upper connection pad.
The drawings are objected to under 37 CFR 1.83(a) because they fail to show the following features as described in the specification.
[0037, 39, 41-46, 58] reference numerals: 152, 154
[0085-88] reference numerals: 220 and 320; 300’
[0101] reference numerals: 300W
Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
[0036] contradicts [0039] regarding whether the wiring structure 140 is disposed on upper or lower surfaces of the first semiconductor chips.
[0106] the features 354 and 364 are base-structure elements; and it seems like this description is intended for pads 154 and insulating layer 164
[0115] the features “upper dummy chip 200 may include a lower bonding insulating layer 210 disposed on an upper surface thereof” should be describing the lower surface of feature 200; and “upper bonding insulating layer 364 of the second semiconductor chip 100” should be describing bonding to upper insulating layer 174
[0071] should be referring to “package 500A” since it is describing Fig. 5
Appropriate correction is required.
Claim Objections
Claim 10 is objected to because of the following informalities:
Regarding Claim 10, the applicant recites “wherein the cover chip further comprises a lower dummy chip” and the disclosure provides only a cover chip 100C that must necessarily be mapped to both the cover chip and the lower dummy chip. The examiner suggests reciting that the cover chip is a lower dummy chip.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 5 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement.
The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 5, the applicant recites “the first upper insulating layer of each of the plurality of first semiconductor chips is directly bonded to the first lower insulating layer of another first semiconductor chip, among the plurality of first semiconductor chips, adjacent thereto,” which appears to align with 100A1 and 100A2. However chip 100A3 does not follow support this recitation, as its top layer is bonded to a cover chip 100C.
The examiner also observes that claim 1 provides an exception for the unique bonding of chip 100A3 (“except for the uppermost first semiconductor chip”) and for the sake of compact prosecution, the examiner imagines that was intended in claim 5 also.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16, 18, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 16, the applicant recites “wherein the second lower insulating layer of the second semiconductor chip is directly bonded to the first lower insulating layer of the uppermost first semiconductor chip.” However, the examiner does not see how that would be geometrically possible and believes this may be an error. For the sake of compact prosecution, the examiner interprets this as “wherein the second lower insulating layer of the second semiconductor chip is directly bonded to the first upper insulating layer of the uppermost first semiconductor chip”.
Regarding Claim 20, essentially the same issue and solution as the indefinite issue of claim 16.
Regarding Claim 18, the applicant recites “wherein the first lower pad of the lowermost first semiconductor chip is directly bonded to the first upper pad.” However, the examiner does not see how that would be geometrically possible and believes this may be an error. For the sake of compact prosecution, the examiner interprets this as “wherein the first lower pad of the lowermost first semiconductor chip is directly bonded to the upper connection pad”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US # 20230133116) in view of Chang (US # 20230082912) and further in view of Uzoh (US # 20200411483).
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Regarding Claim 1, Jang teaches a semiconductor package comprising:
a base structure (100, 600) comprising a lower surface with a lower connection pad (650, 620 on bottom) thereon, and an upper surface with an upper connection pad (322; see Fig. 5A for details; and see also [0128]) thereon, wherein the upper connection pad is connected to the lower connection pad (connected through 120);
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a plurality of first semiconductor chips (three chips 200 are shown in Fig. 1A) stacked on the base structure in a vertical direction (shown), wherein the plurality of first semiconductor chips comprises an uppermost first semiconductor chip (the chip 200 below 200H) and a lowermost first semiconductor chip (200L), and wherein each of the plurality of first semiconductor chips comprises a first lower pad (324; see Fig. 5A), a first upper pad (322; [0130]), and a through silicon via (220) connecting the first lower pad to the first upper pad (shown);
a cover chip (200H) on the plurality of first semiconductor chips, the cover chip comprising an upper surface (inactive surface of substrate 210), wherein the upper surface comprises a flat region (central top surface of 210 and also 350R)
an upper dummy chip (400) disposed on the flat region of the cover chip, the upper dummy chip comprising an area smaller than an area of the cover chip (W3 vs. W2) and a thickness greater than a thickness of the cover chip (H3 vs H2; shown in Fig. 1A and see also [0047-48]),
wherein the first lower pad of the lowermost first semiconductor chip is directly connected to the upper connection pad (pads 324 of chip 200L and top chip pads 322 of chip 200; integrated to form pads 320), and
wherein the first upper pad of each of the plurality of first semiconductor chips, except for the uppermost first semiconductor chip, is directly connected to the first lower pad of another first semiconductor chip, among the plurality of first semiconductor chips, adjacent thereto (320 is between two adjacent chips 200, same diffusion bonding).
Although Jang discloses much of the claimed invention, it does not explicitly teach the cover chip comprising an edge region having a rounded shape, and wherein the edge region is disposed around the flat region.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Chang is in the same or analogous field, and it teaches a cover chip (140) comprising an edge region having a rounded shape (top surface 140 connecting with rounded edge 141 to side surface 143), and wherein the edge region is disposed around the flat region ([0041]). Chang also teaches that this rounding treatment is applicable to the edge of the semiconductor chips ([0069]).
A person having ordinary skill in the art would have recognized that modifying the cover chip of Jang with the trimmed edges suggested by Chang would be obvious. Specifically, the modification suggested by Chang would be to employ a cover chip comprising an edge region having a rounded shape, and wherein the edge region is disposed around the flat region. The rationale for this obvious modification is that rounded shape provides reduction in cracking and chipping (for example see Uzoh at [0075-77]).
Regarding Claim 2, Jang teaches the semiconductor package of claim 1, wherein the base structure further comprises a first area (area of W1), and wherein each of the plurality of first semiconductor chips comprises a second area (area of W2) smaller than the first area (see Fig. 1; W2 < W1]).
Regarding Claim 3, Jang teaches the semiconductor package of claim 2, further comprising: a molding portion (500) disposed on the base structure and surrounding the plurality of first semiconductor chips, the cover chip, and the upper dummy chip (Fig. 1).
Regarding Claim 4, Jang teaches the semiconductor package of claim 3, wherein an upper surface of the upper dummy chip (400) is substantially coplanar with an upper surface of the molding portion (500; see Fig. 1).
Regarding Claim 5, Jang teaches the semiconductor package of claim 1,
wherein each of the plurality of first semiconductor chips (200) further comprises:
a first lower insulating layer (304; see Fig. 5A) on a lower surface thereof and surrounding a side surface of the first lower pad (324); and
a first upper insulating layer (302) disposed on an upper surface thereof and surrounding a side surface of the first upper pad (322), and
wherein the first upper insulating layer of each the plurality of first semiconductor chips is directly bonded to the first lower insulating layer of another first semiconductor chip, among the plurality of first semiconductor chips, adjacent thereto (302 bonds to the next 200 chip insulation material layer 304; see Fig. 5C).
Regarding Claim 6, Jang teaches the semiconductor package of claim 5,
wherein the base structure further comprises a bonding insulating layer (302L) on the upper surface and surrounding a side surface of the upper connection pad (pads 322 on top of 100), and
wherein the first lower insulating layer of the lowermost first semiconductor chip is directly bonded to the bonding insulating layer (302L bonds to 304).
Regarding Claim 7, Jang teaches the semiconductor package of claim 1,
wherein the cover chip comprises a second semiconductor chip (200H) comprising a second lower pad (324), and
wherein the second lower pad is directly bonded to the first upper pad (322) of the uppermost first semiconductor chip (200 immediate beneath 200H).
Regarding Claim 8, Jang teaches the semiconductor package of claim 7, wherein the second semiconductor chip (200 is the same type as 200H) is of the same type as the plurality of first semiconductor chips (formed by the same process, approximately the same height).
Regarding Claim 9 and 10, the designation applied to claim 1 above places the cover chip (200H) directly on the uppermost first semiconductor chip, leaving no body between them. Claim 9 recites a second semiconductor chip disposed between those two elements and therefore cannot be met on that designation; the requirement of an intervening chip is inherent in what claim 9 recites, and any reading of the Jang reference must accordingly designate as the cover chip some body other than the one directly bonded to the uppermost first semiconductor chip. Claims 9 and 10 therefore are rejected on an alternative embodiment of Jang, namely the embodiment of Fig. 2A in which a plurality of supporting dummy substrates 402 is stacked on the second semiconductor chips in place of the single dummy substrate 400. This is the same designation applied to claim 18 below. Under it: base structure (mapping unchanged from claim 1), plurality of first semiconductor chips, uppermost and lowermost (mapping unchanged from claim 1), second semiconductor chip (chip 200H), cover chip (lowermost supporting dummy substrate 402), upper dummy chip (supporting dummy substrate 402, stacked immediately above the cover chip).
Every limitation of claim 1 is met under this alternative designation.
Furthermore, regarding claim 9, Jang further teaches the semiconductor package of claim 1, further comprising:
a second semiconductor chip (uppermost second semiconductor chip 200H) disposed between the uppermost first semiconductor chip (200) and the cover chip (lowermost supporting dummy substrate 402), the second semiconductor chip comprising a second lower pad (324) on a lower surface (sitting on the bottom surfaces) thereof,
wherein the second lower pad of the second semiconductor chip is directly bonded to the first upper pad of the uppermost first semiconductor chip (324 are bonded to pads 322 immediately beneath; see Figs. 5A-5C).
Regarding claim 10, insofar as the claim scope can be ascertained in view of the 35 USC 112 rejections and/or claim objections above, Jang further teaches wherein the cover chip further comprises a lower dummy chip (lower most supporting dummy substrate 402, attached to the uppermost second semiconductor chip 200H by the lowermost supporting coupling insulation layer 352L and carrying a further supporting dummy substrate 402 above it, the supporting dummy substrates including only a semiconductor material and each being a part of a bare wafer; Figs. 2A, 8A-8D). Jang teaches that they are attached by diffusion bonding of a top coupling insulation material (362) to a bottom dummy coupling insulation material layer (364) to form a supporting coupling insulation layer (352).
Regarding claim 11, Jang teaches the semiconductor package of claim 1, wherein the base structure further comprises an base RDL (600; Fig. 1A) comprising an internal wiring layer (620, 640) connecting the lower connection pad (650) to the upper connection pad (150, and then 120 to 322).
Although Jang discloses much of the claimed invention, it does not explicitly teach the base structure further comprises an interposer substrate.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Uzoh is in the same or analogous field, and it teaches a base structure further comprises an interposer substrate (substrate 104 is direct-bonded to a stack including “package substrate, die, wafer, carrier, etc” (see Fig. 2 and corresponding text)).
A person having ordinary skill in the art would have recognized that modifying the base RDL of Jang in view of Chang with the interposer substrate suggested by Uzoh would be obvious. Specifically, the modification suggested by Uzoh would be to employ a base structure further comprises an interposer substrate. This would be merely a simple selection between art-recognized alternatives, performing the same basic functions and yielding predictable results.
Regarding claim 12, Jang further teaches the semiconductor package of claim 1, wherein the base structure further comprises a lower semiconductor chip (110) comprising a through-via (120) connecting the lower connection pad (600, 650, 130, 150) to the upper connection pad (322).
Regarding claim 13, Jang further teaches the semiconductor package of claim 12, wherein each of the plurality of first semiconductor chips comprises a memory chip (chips 200 are DRAM dies), and wherein the lower semiconductor chip comprises a memory control chip (HBM controller die; [0031]).
Regarding claim 14, Jang teaches a semiconductor package comprising:
a base structure (100 and 600; see Fig. 1A) comprising a lower surface with a lower connection pad (650) thereon, and an upper surface with an upper connection pad (322; see Fig. 5A) thereon, wherein the upper connection pad is connected to the lower connection pad (shown connected by features 120);
a plurality of first semiconductor chips (200) stacked on the base structure in a vertical direction (shown), wherein the plurality of first semiconductor chips comprises an uppermost first semiconductor chip (chip 200 immediately below 200H) and a lowermost first semiconductor chip (chip 200L), and wherein each of the plurality of first semiconductor chips comprise a first lower pad (324), a first upper pad (322), and a through silicon via (220) connecting the first lower pad and the first upper pad (shown);
a second semiconductor chip (uppermost chip 200H in Fig. 1A) on the uppermost first semiconductor chip (shown), the second semiconductor chip comprising: a second lower pad (324) directly bonded to the first upper pad (322) of the uppermost first semiconductor chip; and an upper surface comprising a flat region (planar top surface)
an upper dummy chip (supporting dummy substrate 400; Fig. 1A) on the flat region of the second semiconductor chip (stacked on 200H with 350 between), the upper dummy chip comprising an area smaller than an area of the second semiconductor chip (W3<W2) and a thickness greater than a thickness of the second semiconductor chip (H3>H2),
wherein the first lower pad of the lowermost first semiconductor chip is directly connected to the upper connection pad (320 formed by bonding pads 324 and pads 322), and
wherein the first upper pad of each of the plurality of first semiconductor chips, except for the uppermost first semiconductor chip, is directly connected to the first lower pad of another first semiconductor chip, among the plurality of first semiconductor chips, adjacent thereto (pads 320 are coupled between the chips 200).
Although Jang discloses much of the claimed invention, it does not explicitly teach the cover chip comprising an edge region having a rounded shape, and wherein the edge region is disposed around the flat region.
Nonetheless, this would have been render obvious in view of Chang and Uzoh, as already explained in the rejection of claim 1.
Regarding claim 15, Jang teaches the semiconductor package of claim 14,
wherein the base structure further comprises an upper bonding insulating layer (302L) on the upper surface and surrounding a side surface of the upper connection pad (322),
wherein each of the plurality of first semiconductor chips further comprises:
a first lower insulating layer (304) on a lower surface thereof and surrounding a side surface of the first lower pad (324); and
a first upper insulating layer (302) on an upper surface thereof and surrounding a side surface of the first upper pad (322),
wherein the first lower insulating layer of the lowermost first semiconductor chip is directly bonded to the upper bonding insulating layer (see Figs. 5 and corresponding text), and
wherein the first upper insulating layer of each of the plurality of first semiconductor chips, except for the uppermost first semiconductor chip, is directly bonded to the first lower insulating layer of another first semiconductor chip, among the plurality of first semiconductor chips, adjacent thereto (top chip layer 302 and bottom chip layer 304 are diffusion bonded to form a resulting layer 300).
Regarding claim 16, insofar as the claim scope can be ascertained in view of the 35 USC 112 rejections and/or claim objections above, Jang teaches the semiconductor package of claim 15,
wherein the second semiconductor chip comprises a second lower insulating layer (304) on a lower surface thereof and surrounding a side surface of the second lower pad (324), and a second upper insulating layer (302) on an upper surface (top surface of uppermost chip 200H; see Fig. 5D) thereof, and
wherein the second lower insulating layer of the second semiconductor chip is directly bonded to the first lower insulating layer of the uppermost first semiconductor chip (304 and 302 are combined to form layer 300).
Regarding claim 17, Jang teaches the semiconductor package of claim 16, wherein the upper dummy chip comprises a lower bonding insulating layer to which the second upper insulating layer is directly bonded.
Regarding claim 18, insofar as the claim scope can be ascertained in view of the 35 USC 112 rejections and/or claim objections above, Jang teaches the semiconductor package comprising:
a base structure (100 and 600; see Fig. 2A and 4A) comprising a lower surface with a lower connection pad (650) thereon, and an upper surface with an upper connection pad (322; see Fig. 5A and [00128]) thereon, wherein the upper connection pad is connected to the lower connection pad (120, 600, 130);
a plurality of first semiconductor chips (200 chips below 200H) stacked on the base structure in a vertical direction, wherein the plurality of first semiconductor chips comprises an uppermost first semiconductor chip (chip 200 immediately beneath 200H) and a lowermost first semiconductor chip (200L), and wherein each of the plurality of first semiconductor chips comprise a first lower pad (324), a first upper pad (322), and a through silicon via (220) connecting the first lower pad to the first upper pad;
a second semiconductor chip (uppermost 200H) disposed on the uppermost first semiconductor chip, the second semiconductor chip comprising a second lower pad (324) directly bonded to the first upper pad of the uppermost first semiconductor chip (322 and 324 are bonded to form a unified pad 320);
a lower dummy chip (lowermost 402/404) disposed on the second semiconductor chip, the lower dummy chip comprising an upper surface, wherein the upper surface comprises a flat region (planar top surface)
an upper dummy chip (402/404H/404aH) disposed on the flat region of the lower dummy chip,
wherein the first lower pad of the lowermost first semiconductor chip is directly bonded to the first upper pad (320 formed by combining 324 and 322), and
wherein the first upper pad of each the plurality of first semiconductor chips, except for the uppermost first semiconductor chip, is directly bonded to the first lower pad of another first semiconductor chip, among the plurality of first semiconductor chips, adjacent thereto (320 is the pads combined between the chips 200).
Although Jang discloses much of the claimed invention, it does not explicitly teach the cover chip comprising an edge region having a rounded shape, and wherein the edge region is disposed around the flat region.
Nonetheless, this would have been render obvious in view of Chang and Uzoh, as already explained in the rejection of claim 1.
Furthermore, unlike in claim 1, Jang fails to teach the upper dummy chip wherein the upper dummy chip comprises an area smaller than an area of the lower dummy chip.
However Uzoh also teaches that the prepared bonding surface of the top die 1904 is made smaller than the bonding surface of the die beneath it, forming a peripheral gap beyond the bonded region that an encapsulant wedge or fillet (1906) may fill (see Fig. 19 and corresponding text).
A person having ordinary skill in the art at the time of filing would have given the uppermost supporting dummy substrate (Jang, features 404H/404aH) an area smaller than that of the lowermost supporting dummy substrate beneath it because Uzoh teaches that reducing the bonded area reduced the force transmitted to the bonded died beneath and because Jang uses that same area relationship itself (W3 < the width of the body beneath it). The allows the edge to serve as an alignment enhancer. For these reasons, the combination of prior-art teachings would have rendered the claimed limitations obvious.
Regarding claim 19, Jang teaches the semiconductor package of claim 18,
wherein the base structure further comprises an upper bonding insulating layer (302L) disposed on the upper surface and surrounding a side surface of the upper connection pad (322),
wherein each of the plurality of first semiconductor chips further comprises:
a first lower insulating layer (304) on a lower surface thereof and surrounding a side surface of the first lower pad (324); and
a first upper insulating layer (302) on an upper surface thereof and surrounding a side surface of the first upper pad (322),
wherein the first lower insulating layer of the lowermost first semiconductor chip is directly bonded to the upper bonding insulating layer (302L bonds with 304 to form 300L), and
wherein the first upper insulating layer of each the plurality of first semiconductor chips, except for the uppermost first semiconductor chip, is directly bonded to the first lower insulating layer of another first semiconductor chip, among the plurality of first semiconductor chips, adjacent thereto (302 and 304 for to make layer 300; see Fig. 2A).
Regarding claim 20, insofar as the claim scope can be ascertained in view of the 35 USC 112 rejections and/or claim objections above, Jang teaches the semiconductor package of claim 19,
wherein the second semiconductor chip further comprises:
a second lower insulating layer (304 on uppermost 200H) on a lower surface thereof and surrounding a side surface of the second lower pad, and
a second upper insulating layer (302 on uppermost 200H, forms part of 352L; see Figs. 5D and 8A) on an upper surface thereof, and
wherein the second lower insulating layer is directly bonded to the first lower insulating layer of the uppermost first semiconductor chip (302 forms layer 300).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4, 8, 11, 13, 17, 18, and 20 of U.S. Patent No. 12347819 in view of Chang (US # 20230082912).
Although claim 1 of the ‘819 patent recites much of the claimed invention, it does not recite the cover chip comprising the upper surface, wherein the upper surface comprises a flat region and an edge region having a rounded shape, and wherein the edge region is disposed around the flat region.
Nonetheless the prior art at the time the application was filed, in the same field of endeavor, renders such feature differences obvious, as explained below.
For example, Chang is in the same or analogous field, and it teaches a cover chip (140) comprising an edge region having a rounded shape (top surface 140 connecting with rounded edge 141 to side surface 143), and wherein the edge region is disposed around the flat region ([0041]). Chang also teaches that this rounding treatment is applicable to the edge of the semiconductor chips ([0069]). The rationale for this obviousness conclusion was already provided in the rejection of claim 1 under the 35 USC 103 heading above.
Claim 14 of the application is aligned with patented claims 1, 2, 11, and 12. And further, the obviousness conclusion is established by the claim 1 rejection.
Claim 2 aligns with patented claim 8.
Claims 3 and 4 align with patented claim 17.
Claims 5, 6, 15, and 16 align with patented claims 1, 13, 18, and 20.
Claims 7 and 8 align with patented claims 1, 2, 11, and 12.
Claims 9 and 10 align with patented claims 1 and 5.
Claim 11 aligns with patented claim 17.
Claim 12 aligns with patented claim 1.
Claim 13 aligns with patented claim 11.
Claim 17 aligns with patented claim 1.
Claims 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4-6, 8, 13, 18, and 20 of U.S. Patent No. 12347819 in view of Chang (US # 20230082912).
Claim 18 aligns with patented claims 1, 5, 6, and 7. The limitations regarding the relative thicknesses and relative areas of the chips is obvious in view of Chang, as explained above in the prior art rejections.
Claims 19 and 20 align with patented claims 1, 13, 18, and 20.
Claims 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 19219758 in view of Chang (US # 20230082912).
This is a provisional nonstatutory double patenting rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time.
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/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899
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