DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form
(http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1, 5 and 9.
b. Pending: 1-15.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim PG PUB 20170031747 (hereinafter Kim), supported by NAKAMURA PG PUB 20110099459 (hereinafter NAKAMURA).
Regarding independent claim 1, Kim teaches a semiconductor apparatus (title of Kim, [0050] of Kim, “…a semiconductor system according to an embodiment may include a first semiconductor device 1 and a second semiconductor device 2…”) comprising:
a parity operation circuit (200 in figure 5, 600 in figure 11) configured to generate a parity signal by performing an operation on operation source data ([0061], “…error corrector 200 may generate correction parity bits EC_P<1:M> including the error information on the internal data ID<1:K> in synchronization with the first delayed strobe signal STRD1 during the write operation…”, [0119] of Kim, “… error corrector 600 may generate correction parity bits EC_P<1:M> including the error information on the internal data ID…”);
a write latch circuit (210 in figure 6, first buffer 610 indicated in [0146] of Kim, [0083], “…first buffer 210 may include an initializer 211, a first transmitter 212 and a second transmitter 213…”, [0086], “…second transmitter 213 may latch a signal of the node ND21… to generate the internal parity bits IP<1:M>…”) configured to generate a write parity signal by latching the parity signal according to a delayed write signal (Kim teaches delayed strobe signals used to control timing of parity and data output, [0118] of Kim, “…first repeater 500 may generate the internal data ID<1:K> from the data D<1:K> in synchronization with the first strobe signal STR1 and may delay the first strobe signal STR1 to generate a first delayed strobe signal STRD1…”, [0146] of Kim, “…first buffer 610 may output the parity bits P<1:M> as the internal parity bits IP<1: M> in response to the first delayed strobe signal STRD1 and the second strobe signal STR2…”);
a data processing circuit configured to output write data as the operation source data in a write operation, and configured to delay the operation source data by a time required for operation of the parity signal and output it as delayed data (Kim teaches delaying internal data via repeater circuits and coordinating data timing with delayed strobe signals, [0155], “…first repeater 500 may also generate the internal data ID<1:K> from the data D<1:K>…”, [0136], “… second buffer 620 may output the internal data ID<1:K> as the correction data EC_ID<1:K> in response to the first delayed strobe signal STRD1 and the second strobe signal STR2…”, thus data is delayed and synchronized with parity timing during write operations); and
a write path configured to write the delayed data and the write parity signal to a memory area in the write operation (Kim teaches writing both internal data and parity bits to memory, [0158], “… first memory portion 50 may store the parity bits P<1:M> and the internal data ID<1:K>...”)
Regarding claim 2, Kim teaches the semiconductor apparatus of claim 1, wherein the delayed write signal is generated by delaying a write command provided from outside the semiconductor apparatus by an operation time of the parity operation circuit (Kim teaches generation of delayed strobe/control signals by synchronizing with correction/parity processing time, Kim teaches that external write data and strobe signals are input and internal delayers to align with error correction and parity operation, Kim further teaches generation of delayered strobe signals through repeaters and delay circuit to match parity correction timing, [0094], “…the first semiconductor device 1 may output the external strobe signal ESTR and the external data ED<1:K>…”, [0017], “… first repeater suitable for blocking input of at least one of the data according to a masking signal, suitable for generating the internal data from the data in synchronization with the first strobe signal, and suitable for delaying the first strobe signal to generate a first internal strobe signal and a first delayed strobe signal… third repeater suitable for generating a second delayed strobe signal by delaying the first correction strobe signal and suitable for outputting the first correction data as the data…”, these passages expressly teach delaying an external provide write related control signal (strobe/write command) by a time associated with parity/correction circuitry operation in order to synchronize write data and parity generation).
Regarding claim 3, Kim teaches the semiconductor apparatus of claim 1, wherein the write latch circuit is configured to initialize the write parity signal to a predetermined level upon activation of a reset signal (Kim teaches initialization and reset behavior of correction/parity circuits and internal latch structure, claim 7, “…a first error corrector suitable for generating first correction parity bits…”, claim 9, “…a first buffer suitable for outputting the first parity bits…”, as understood by one of ordinary skill in the art, parity/correction buffers and latch circuits are necessarily reset to a known predetermined logic level prior to operation. It would have been obvious to initialize the parity letch to a predestined level upon reset) and, after deactivation of the reset signal, configured to latch the parity signal upon activation of the delayed write signal and output as the write parity signal (Kim teaches latching parity bits in synchronization with delayered strobe signals, [0017], “…first error corrector suitable for generating first correction parity bits including error information on the internal data in synchronization with the first delayed strobe signal…”)
Regarding claim 4, Kim teaches the semiconductor apparatus of claim 1, wherein the write path comprises: a global line configured to transmit the write data to the data processing circuit (Kim teaches I/O lines and internal data transmission paths between peripheral circuitry and memory); and a write driver configured to drive the delayed data and the write parity signal to be written to the memory area (Kim teaches circuitry for outputting corrected data and parity information via repeaters and buffers, which function as drivers).
Claims 5-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over NAKAMURA PG PUB 20110099459 (hereinafter NAKAMURA), supported by Kim PG PUB 20170031747 (hereinafter Kim).
Regarding independent claim 5, NAKAMURA teaches a semiconductor apparatus comprising:
a parity operation circuit (ECC circuit 1002 in [0009], “…ECC circuit 1002 includes a syndrome generation circuit 1002a, an error detection circuit 1002b, an error correction circuit 1002c, and a parity generation circuit 1002d…”) configured to generate a parity signal by performing an operation on operation source data;
a read latch circuit (1001 in [0009] and [0052], “…a read latch circuit 1001…”, [0057], a read signal RYPA is delayed through dummy ECC circuit 105 to generate timing aligned with ECC processing, [0069], “…read data output signal RDOUT is generated by the read signal RYPA being passed through the dummy ECC read circuit 202…”) configured to generate a read parity signal by latching the parity signal according to a delayed read signal;
a syndrome operation circuit (“syndrome generation circuit 102a” in [0053], “…the syndrome … is input to the error detection circuit 102b…to generate an error flag ERR…”) configured to generate an error correction flag according to the read parity signal;
a data processing circuit configured to output read data output from a memory area in a read operation as the operation source data, and configured to delay the operation source data by a time required for operation of the parity signal and the error correction flag and output it as delayed data (Nakamura teaches in [0012]/[0013] that ECC processes introduce delay, write and read signals are delayed by a dummy ECC circuit that replicates the ECC processing delay, timing control signal generator delays control signals by a period corresponding to delay time of ECC circuit, [0017], “…timing control signal generator includes a circuit which is the same as or corresponds to at least a portion of the error correction code circuit, and is configured to delay a timing of the first timing control signal by a period of time corresponding to a delay time of the error correction code circuit, and output the second timing control signal, depending on the delayed timing of the first timing control signal…”, Under BRI, delaying the read output timing (ROUT) to correspond to ECC processing time constitutes delaying the effective output of the operation source data by the time required for parity and error correction operation); and
a read path configured to correct errors of the delayed data according to the error correction flag and output it in the read operation (Nakamura teaches error correction circuit 102c perform correction based on error flag, corrected read data is output via latch 103).
Regarding claim 6, NAKAMURA teaches the semiconductor apparatus of claim 5, wherein the delayed read signal is generated by delaying a read command provided from outside the semiconductor apparatus by an operation time of the parity operation circuit (Nakamura teaches external read command generate read signal RYPA, RYPA is delayed via dummy ECC circuit corresponding to ECC processing time).
Regarding claim 7, NAKAMURA teaches the semiconductor apparatus of claim 5, wherein the read latch circuit (read latch 101 in [0052]) is configured to initialize the read parity signal to a predetermined level upon activation of a reset signal and, after deactivation of the reset signal, configured to latch the parity signal upon activation of the delayed read signal and output as the read parity signal (it is well-known and inherent in latch circuits that latches are initialized by reset, latch output depends on control signal activation).
Regarding claim 8, NAKAMURA teaches the semiconductor apparatus of claim 5, wherein the read path comprises: a sense/amplification circuit configured to sense and amplify the read data and a parity signal corresponding to the read data ([0051], “…Data read out to bit lines are sensed and amplified by sense amplifiers, and selectively read out via switch gates to a large number of normal data lines DL; and parity data lines PDL…”); a global line configured to transmit an output of the sense/amplification circuit to the data processing circuit ([0051], “…Data read out to bit lines are sensed and amplified by sense amplifiers, and selectively read out via switch gates to a large number of normal data lines DL; and parity data lines PDL…”); and a data correction circuit (ECC circuit 102 including error correction circuit 102c, [0053]) configured to correct errors contained in the delayed data in accordance with the error correction flag.
Regarding independent claim 9, NAKAMURA teaches a semiconductor apparatus comprising: a parity operation circuit (a parity generation circuit 102d in [0089], ECC circuit 1002 in [0009], “…ECC circuit 1002 includes a syndrome generation circuit 1002a, an error detection circuit 1002b, an error correction circuit 1002c, and a parity generation circuit 1002d…”) configured to generate a parity signal by performing an operation on operation source data;
a write latch circuit (write buffer 104 in [0089]) configured to generate a write parity signal by latching the parity signal according to a delayed write signal (Nakamura teaches a write buffer circuit 104 and a dummy ECC circuit that generates write signal WYPA after a delay corresponding to ECC processing time);
a read latch circuit (data latch/input/output circuit 103 in [0089], 1001 in [0009] and [0052], “…a read latch circuit 1001…”, [0057], a read signal RYPA is delayed through dummy ECC circuit 105 to generate timing aligned with ECC processing, [0069], “…read data output signal RDOUT is generated by the read signal RYPA being passed through the dummy ECC read circuit 202…”) configured to generate a read parity signal by latching the parity signal according to a delayed read signal;
a syndrome operation circuit (“syndrome generation circuit 102a” in [0053], “…the syndrome … is input to the error detection circuit 102b…to generate an error flag ERR…”) configured to generate an error correction flag in accordance with the read parity signal;
a data processing circuit configured to output write data provided from outside of the semiconductor apparatus as the operation source data ([0063], eternal write data WDIN input to data latch and parity generation circuit) and configured to delay the operation source data by a first time required for operation of the parity signal and output it as a first delayed data in a write operation (Nakamura teaches in [0061]/[0077] that write signal delayed by dummy ECC circuit to match ECC delay), and configured to output read data output from a memory area as the operation source data and configured to delay the operation source data by a second time required for operation of the parity signal and the error correction flag and output it as second delayed data in a read operation (Nakamura teaches in [0068]/[0069] that read data output delayed via dummy ECC read circuit 202);
a write path (write buffer circuit 104 in [0063] that write normal write data WD and parity data PWD to memory array) configured to write the first delayed data and the write parity signal to the memory area in the write operation; and a read path (Nakamura teaches in [0053] that error correction circuit 102c corrects read data according to error flag) configured to correct errors of the second delayed data according to the error correction flag in the read operation.
Regarding claim 10, NAKAMURA teaches the semiconductor apparatus of claim 9, wherein the delayed write signal is generated by delaying a write command provided from outside the semiconductor apparatus by an operation time of the parity operation circuit ([0061], “…the write signal WYPA is generated by delaying the read signal RYPA by a time corresponding to the time which it takes for the read signal RYPA to pass through the ECC circuit 102…”)
Regarding claim 11, NAKAMURA teaches the semiconductor apparatus of claim 9, wherein the delayed read signal is generated by delaying a read command provided from outside the semiconductor apparatus by an operation time of the parity operation circuit ([0068]/[0069], Nakamura teaches read output signal RDOUT generated via dummy ECC read circuit producing ECC-equivalent delay).
Regarding claim 12, NAKAMURA teaches the semiconductor apparatus of claim 9, wherein the write latch circuit is configured to initialize the write parity signal to a predetermined level upon activation of a reset signal and, after deactivation of the reset signal, configured to latch the parity signal upon activation of the delayed write signal and output as the write parity signal (it is well-known and inherent in latch circuits that latches are initialized by reset, latch output depends on control signal activation, alternatively, Kim teaches initialization /reset of latch circuits for parity handling).
Regarding claim 13, NAKAMURA teaches the semiconductor apparatus of claim 9, wherein the read latch circuit is configured to initialize the read parity signal to a predetermined level upon activation of a reset signal and, after deactivation of the reset signal, configured to latch the parity signal upon activation of the delayed read signal and output as the read parity signal (it is well-known and inherent in latch circuits that latches are initialized by reset, latch output depends on control signal activation).
Regarding claim 14, NAKAMURA teaches the semiconductor apparatus of claim 9, wherein the write path comprises: a global line configured to transmit the write data to the data processing circuit; and a write driver configured to drive the first delayed data and the write parity signal to be written to the memory area (Nakamura teaches in [0051]-[0056] write buffer 104 drives write data and parity data to memory array).
Regarding claim 15, NAKAMURA teaches the semiconductor apparatus of claim 9, wherein the read path comprises: a sense/amplification circuit configured to sense and amplify the read data and a parity signal corresponding to the read data; a global line configured to transmit an output of the sense/amplification circuit to the data processing circuit; and a data correction circuit configured to correct errors contained in the second delayed data in accordance with the error correction flag (Nakamura teaches in [0051] a sense amplifier 101, in [0053] an ECC correction circuit 102c corrects read data, data is transmitted via data latch/input/output circuit 103).
Conclusion
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824