Prosecution Insights
Last updated: October 25, 2026
Application No. 18/678,698

THREE-DIMENSIONAL STACKED DRAM DEVICE WITH SUB 4F2 STRUCTURE CELLS

Non-Final OA §112
Filed
May 30, 2024
Examiner
JUNG, MICHAEL YOO LIM
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taesung Environmental Research Institute Co. Ltd.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
1072 granted / 1295 resolved
+14.8% vs TC avg
Moderate +10% lift
Without
With
+10.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
22 currently pending
Career history
1326
Total Applications
across all art units

Statute-Specific Performance

§101
2.4%
-37.6% vs TC avg
§103
30.7%
-9.3% vs TC avg
§102
33.4%
-6.6% vs TC avg
§112
28.8%
-11.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1295 resolved cases

Office Action

§112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Currently, claims 1-4 are pending and examined below. Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Section 2173.02.I. of the MPEP provides the following guidance on how pre-issuance claims under examination are construed differently than patented claims: Patented claims are not given the broadest reasonable interpretation during court proceedings involving infringement and validity, and can be interpreted based on a fully developed prosecution record. While "absolute precision is unattainable" in patented claims, the definiteness requirement "mandates clarity." Nautilus, Inc. v. Biosig Instruments, Inc., 527 U.S. __, 134 S. Ct. 2120, 2129, 110 USPQ2d 1688, 1693 (2014). A court will not find a patented claim indefinite unless the claim interpreted in light of the specification and the prosecution history fails to "inform those skilled in the art about the scope of the invention with reasonable certainty." Id. at 1689. PNG media_image1.png 18 19 media_image1.png Greyscale The Office does not interpret claims when examining patent applications in the same manner as the courts. In re Packard, 751 F.3d 1307, 1312, 110 USPQ2d 1785, 1788 (Fed. Cir. 2014); In re Morris, 127 F.3d 1048, 1054, 44 USPQ2d 1023, 1028 (Fed. Cir. 1997); In re Zletz, 893 F.2d 319, 321-22 (Fed. Cir. 1989). The Office construes claims by giving them their broadest reasonable interpretation during prosecution in an effort to establish a clear record of what the applicant intends to claim. Such claim construction during prosecution may effectively result in a lower threshold for ambiguity than a court's determination. Packard, 751 F.3d at 1323-24, 110 USPQ2d at 1796-97 (Plager, J., concurring). However, applicant has the ability to amend the claims during prosecution to ensure that the meaning of the language is clear and definite prior to issuance or provide a persuasive explanation (with evidence as necessary) that a person of ordinary skill in the art would not consider the claim language unclear. In re Buszard, 504 F.3d 1364, 1366 (Fed. Cir. 2007)( claims are given their broadest reasonable interpretation during prosecution "to facilitate sharpening and clarifying the claims at the application stage"); see also In re Yamamoto, 740 F.2d 1569, 1571 (Fed. Cir. 1984); In re Zletz, 893 F.2d 319, 322, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989). Here, the independent claim 1 is indefinite for two reasons: First, it is unclear whether “the first conductive line” refers to all of “a plurality of first conductive lines” or just one of the “plurality of first conductive lines.” Second, “the single first conductive line” lacks antecedent basis. For the purpose of advancing the examination of the instant application, “the first conductive line” and “the single first conductive line” have been interpreted as referring to just one of the “plurality of first conductive lines.” Claim 2 is indefinite, because it depends from the indefinite independent claim 1. Independent claim 3 is indefinite for the same two reasons that the independent claim 1 is indefinite. In addition, the independent claim 3 if further indefinite, because “the third conductive line” lacks antecedent basis. Claim 4 is indefinite, because it depends from the indefinite independent claim 3. Allowable Subject Matter The following is a statement of reasons for the indication of allowable subject matter: But for its pending 35 U.S.C. 112(b) rejection, the independent claim 1 would be allowable. PNG media_image2.png 504 753 media_image2.png Greyscale Regarding independent claim 1, Chen (Pub. No. US 2024/0407151 A1 to Chen et al.) teaches a DRAM device (see Fig. 8A for example), comprising: a substrate SiSub (para [0109] - “a silicon substrate SiSub.”); a plurality of first conductive lines 841 (para [0102] - “multiple conductive plugs 841”) oriented in a first direction perpendicular Z to an upper surface of the substrate SiSub, and disposed parallel to each other at predetermined intervals, a plurality of second conductive lines 820, 830 (para [0103] - “…the disposed positions of two adjacent first conductive structures 820 are staggered from each other, and the disposed positions of two adjacent second conductive structures 830 are also staggered from each other, as shown in FIG. 8B.”) located (indirectly) on the first conductive lines 841, and disposed parallel to each other in a second direction perpendicular X to the first conductive line 841 at predetermined intervals, a plurality of channel patterns 810 each extending in a third direction Y perpendicular to both the first direction Z and the second direction X, and a gate insulating pattern CI1-Cl4 (para [0072] - “multiple dielectric layers CI1 to CI4”) located on the plurality of channel patterns 810; wherein the plurality of second conductive lines 820, 830 comprises a first subline 820 and a second subline 830 which are at different distances from the first conductive line 841, and the first subline 820 and the second subline 830 are provided alternating with each other in the first direction Z. Nevertheless, the independent claim 1 is allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 1, a plurality of channel patterns arranged in a honeycomb structure on the first conductive line; a gate insulating pattern located between the plurality of channel patterns and the plurality of second conductive lines; and the plurality of channel patterns located on the single first conductive line are arranged in zigzag along both edges of the single first conductive line, and the plurality of channel patterns contacting the single second conductive line are arranged in a straight line. Claim 2 is allowable, because it depends from the allowable independent claim 1. Independent claim 3 is allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 3, a plurality of channel patterns arranged in a honeycomb structure on the first conductive line; a gate insulating pattern located between the plurality of channel patterns and the plurality of second conductive lines or the plurality of third conductive lines; and the plurality of channel patterns located on the single first conductive line are arranged in zigzag along both edges of the single first conductive line, and the plurality of channel patterns contacting the single second conductive line or the third conductive line are are arranged in a straight line. Claim 4 is allowable, because it depends from the allowable independent claim 3. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Pub. No. US 2024/0098969 A1 to Hwang et al. Pub. No. US 2023/0413517 A1 to Kim et al. Pub. No. US 2023/0180455 A1 to Choi et al. Pub. No. US 2023/0014052 A1 to Tang Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL JUNG/Primary Examiner, Art Unit 2817 06 June 2026
Read full office action

Prosecution Timeline

May 30, 2024
Application Filed
Jun 10, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE
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SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
93%
With Interview (+10.5%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1295 resolved cases by this examiner. Grant probability derived from career allowance rate.

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