CTNF 18/678,783 CTNF 82250 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-20 are pending in the application. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim(s) 1-7 and 9-19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chang et al. (US 2025/0015161) (hereinafter, “Chang”) . Re: independent claim 1, Chang discloses in fig. 1 a semiconductor device, comprising: an active region (120) formed in a substrate (100); a gate dielectric layer (230) located on the active region and having an extension area (230a) on opposite sides of the gate dielectric layer respectively; a gate electrode (210) located on the gate dielectric layer and exposing the two extension areas; and a source/drain region (250) located in the active region on one side of the gate dielectric layer. Re: claim 2, Chang discloses in fig. 1 the semiconductor device of claim 1, wherein the active region comprises a channel region (CH), a drain extension region (F) and a source extension region (F), and the channel region (CH) is located between the drain extension region (F) and the source extension region (F). Re: claim 3, Chang discloses in fig. 1 the semiconductor device of claim 2, wherein an overlapping area of the gate dielectric layer (230) with the channel region (CH), the drain extension region (F), and the source extension region (F) is greater than an overlapping area of the gate electrode layer (210) with the channel region (CH), the drain extension region (F), and the source extension region (F). Re: claim 4, Chang discloses in fig. 1 the semiconductor device of claim 3, wherein a distance between an edge of the gate dielectric layer (230) and an edge of the gate electrode (210) is a length of each of the extension areas (F). Re: claim 5, Chang discloses in fig. 1 the semiconductor device of claim 4, wherein the length of each of the extension areas (F) is a length of the overlapping area of the gate dielectric layer (230) and the drain extension region (F) minus a length of the overlapping area of the gate electrode (210) and the drain extension region (F). Re: claim 6, Chang discloses in fig. 1 the semiconductor device of claim 4, wherein the edge of the gate dielectric layer (230) is flush with an edge of the source/drain region (250). Re: claim 7, Chang discloses in fig. 1 the semiconductor device of claim 1, further comprising a gate spacer (220) covering sidewalls of the gate electrode (210). Re: independent claim 9, Chang discloses in fig. 1 a semiconductor device, comprising: a drain extension region (F) formed in a substrate (100); a gate dielectric layer (230) located on the drain extension region (F), the gate dielectric layer (230) has an extension area (230a) on one side, and the extension area (230a) overlaps the drain extension region (F); a gate electrode (210) located on the gate dielectric layer (230) and exposing the extension area (230a); and a drain region (250) located in the substrate (100) on the side of the gate dielectric layer (230). Re: claim 10, Chang discloses in fig. 1 the semiconductor device of claim 9, wherein an overlapping area of the gate dielectric layer (230) and the drain extension region (F) is greater than an overlapping area of the gate electrode layer (210) and the drain extension region (F). Re: claim 11, Chang discloses in fig. 1 the semiconductor device of claim 10, wherein a distance between an edge of the gate dielectric layer (230) and an edge of the gate electrode (210) is a length of the extension area (230a). Re: claim 12, Chang discloses in fig. 1 the semiconductor device of claim 11, wherein the edge of the gate dielectric layer (230) is flush with an edge of the drain region (250). Re: independent claim 13, Chang discloses in fig. 1 a method of manufacturing a semiconductor device, comprising: forming an active region (120) in a substrate (100); depositing a gate dielectric layer (230) on the active region, the gate dielectric layer (230) having an extension area (230a) on opposite sides of the gate dielectric layer respectively; forming a gate electrode (210) on the gate dielectric layer (230) and exposing the two extension areas (230a) from the gate electrode (210); and performing an ion implantation [0040] by using the gate dielectric layer (230) as a mask to form a source/drain region (250) located in the active region (102) on one side of the gate dielectric layer (230). Re: claim 14, Chang discloses in fig. 1 the method of claim 13, wherein the active region (120) comprises a channel region (CH), a drain extension region (F) and a source extension region (F), and the channel region (CH) is located between the drain extension region (F) and the source extension region (F). Re: claim 15, Chang discloses in fig. 1 the method of claim 14, wherein an overlapping area of the gate dielectric layer (230) with the channel region (CH), the drain extension region (F), and the source extension region (F) is greater than an overlapping area of the gate electrode layer (210) with the channel region (CH), the drain extension region (F), and the source extension region (F). Re: claim 16, Chang discloses in fig. 1 the method of claim 15, wherein a distance between an edge of the gate dielectric layer (230) and an edge of the gate electrode (210) is a length of each of the extension areas (250). Re: claim 17, Chang discloses in fig. 1 the method of claim 16, wherein the length of each of the extension areas (230a) is a length of the overlapping area of the gate dielectric layer (230) and the drain extension region (F) minus a length of the overlapping area of the gate electrode (210) and the drain extension region (F). Re: claim 18, Chang discloses in fig. 1 the method of claim 16, wherein the edge of the gate dielectric layer (230) is flush with an edge of the source/drain region (250). Re: claim 19, Chang discloses in fig. 1 the method of claim 13, further comprising forming a gate spacer (220) covering sidewalls of the gate electrode (210) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 8 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2025/0015161) (hereinafter, “Chang”) in view of Li et al. (US 2018/0012890) (hereinafter, Li) . Re: claims 8 and 20, Chang discloses in fig. 1 the semiconductor device of claim 1 and the method of claim 13. Chang does not expressly disclose forming at least one interlayer dielectric layer and at least one conductive plug formed in the interlayer dielectric layer, wherein the interlayer dielectric layer covers the active region, and the conductive plug is electrically connected to the source/drain region. Li discloses in fig. 10 forming at least one interlayer dielectric layer (326) and at least one conductive plug (328) formed in the interlayer dielectric layer, wherein the interlayer dielectric layer (326) covers an active region (306), and the conductive plug (328) is electrically connected to a source/drain region (318). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form an interlayer dielectric layer and conductive plug as claimed for the purpose of insulating the device from other components in an integrated circuit and to facilitate connection of the device (Li, [0074]) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chang et al. US 9,922,881 teach a gate dielectric layer including extension areas extending beyond sidewalls of a gate electrode, and source/drain extension region formed under the gate dielectric layer and the gate electrode. The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 6/11/2026 Application/Control Number: 18/678,783 Page 2 Art Unit: 2824 Application/Control Number: 18/678,783 Page 3 Art Unit: 2824 Application/Control Number: 18/678,783 Page 4 Art Unit: 2824 Application/Control Number: 18/678,783 Page 5 Art Unit: 2824 Application/Control Number: 18/678,783 Page 6 Art Unit: 2824 Application/Control Number: 18/678,783 Page 7 Art Unit: 2824 Application/Control Number: 18/678,783 Page 8 Art Unit: 2824
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