Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated December 22, 2025, claims 1-20 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Claim Objections
Claims 4-8, 16 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bruno et al. [FR 2850201 A1].
With respect to claim 1, Bruno et al. disclose a device comprising [“…Address decoder (WLDEC2) for selectively applying to the word lines (WLi, j) of a memory plane (MA)... characterized in that it comprises:…” – claim 1 (Both recitations describe a hardware memory circuit architecture. Reference A explicitly discloses a "comprising" transitional phrase outlining its sub-components (GPGEN, DECGEN, Di,j).)]: a wordline decoder configured to apply a voltage to a wordline [“Address decoder (WLDEC2) for selectively applying to the word lines (WLi, j) of a memory plane (MA) signals (Vi, j)...” – claim 1 (The "Address decoder (WLDEC2)" in the Reference directly matches the "wordline decoder" of the claimed recitation. The "signals (Vij)" inherently represent the electrical "voltage" being applied to the "word lines (WLij)")], wherein a polarity of the voltage is selectable based on a program polarity [“...signals (Vi, j) of variable polarity, negative or positive, whose value is function an address (ADR) of word line applied to the decoder... AND ...delivering word group selection signals (GPi) of word lines which are of variable polarity (VPOS, VNEG)...” – claim 1 (the claimed recitation requires a voltage whose polarity can change ("selectable"). The patent explicitly describes signals of "variable polarity, negative or positive" ((V_POS), (V_NEG). The selection mechanism in Reference A is dictated by the address ((ADR) applied to the decoder and the system state, which functionally achieves selecting a polarity for programming operations.)]; and a controller configured to select the program polarity [“…whose value is function an address (ADR) of word line applied to the decoder... operating alongside group decoder (GPGEN) and sub-group decoder (DECGEN, SPGEN)…” – claim 1 (The decoders (GPGEN, DECGEN) act as the control circuitry that interprets the input address (ADR) and operational mode to actively route and select the negative (V_NEG) or positive ((V_POS) polarity lines via the driver multiplexing means (TP1, TP2, TN1, TN2). It is noted that a circuit configured to perform control logic inherently satisfies a broadly claimed "controller configured to" limitation.)].
With respect to claim 2, Bruno et al. disclose the wordline decoder applies a voltage of a second polarity when operating in a first program polarity; and the wordline decoder applies a voltage of a first polarity when operating in a second program polarity [“Address decoder (WLDEC2) for selectively applying to the word lines (WLi, j) of a memory plane (MA) signals (Vi, j) of variable polarity, negative or positive…” – claim 1].
With respect to claim 3, Bruno et al. the first and second program polarities are opposite [“Address decoder (WLDEC2) for selectively applying to the word lines (WLi, j) of a memory plane (MA) signals (Vi, j) of variable polarity, negative or positive…” – claim 1].
Claim(s) 9-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bruno et al. [FR 2850201 A1].
With respect to claim 9, Bruno et al. disclose an apparatus comprising ["Address decoder (WLDEC2) for selectively applying to the word lines..." – claim 1 (The patent describes an address decoder circuit topology, which structurally qualifies as an electronic apparatus.)]: a first voltage supply ["...variable polarity, negative or positive..." / "variable polarity (VPOS, VNEG)" – claim1 (the patent specifies a positive polarity supply voltage (VPOS). This functions as the first voltage supply.)]; a second voltage supply ["...variable polarity, negative or positive..." / "variable polarity (VPOS, VNEG)" – claim 1 (the patent specifies a negative polarity supply voltage (VNEG). This functions as the second voltage supply.)]; and a controller configured to ["Address decoder (WLDEC2)... comprising: - a group decoder (GPGEN)... - at least one sub-group decoder... and - word line drivers..." – claim 1 (The decoder system as a whole (WLDEC2, GPGEN, DECGEN/SPGEN) controls the routing of signals. It acts as the "controller" steering the voltages based on digital logic inputs.)]: select a polarity ["...signals (Vi, j) of variable polarity, negative or positive, whose value is function an address (ADR)..." – claim 1 (The decoder reads the incoming address (ADR) to determine whether the target operation requires a positive or negative voltage configuration.)]; and select, based on the polarity, the first or second voltage supply ["...each comprising means (TP1, TP2, TN1, TN2) for multiplexing the group and subgroup selection signals... to select and selectively apply one of these signals..." – claim 1 (The multiplexing circuit elements (TP1, TP2, TN1, TN2) dynamically select between the paths tied to the positive ((VPOS) or negative ((VNEG) variable polarity lines based on the determined decoding state. )] for coupling to an access line ["...to a word line (WLi, j)." – claim 1 (an "access line" is the generic term for a word line (which controls access to a row of memory cells). They are functional equivalents.)].
With respect to claim 10, Bruno et al. disclose the polarity is a program polarity [“Address decoder (WLDEC2) for selectively applying to the word lines (WLi, j) of a memory plane (MA) signals (Vi, j) of variable polarity, negative or positive…” – claim 1].
With respect to claim 11, Bruno et al. disclose a switch configured to ["...word line drivers (Di, j)... each comprising means (TP1, TP2, TN1, TN2) for multiplexing..." – claim 1 (A multiplexer is a combination of electronic switches (typically transistors like TP/TN). They act as switches to open or close electrical paths. )] connect the selected voltage supply ["...for multiplexing the group and subgroup selection signals; -group, to select and selectively apply one of these signals..." – claim 1 (The multiplexing transistors connect the specific chosen polarity signal (the voltage supply) to the active circuit path.)] to the access line ["...to a word line." – claim 1 (The final destination of the switched connection is the word line (which is the access line).)].
With respect to claim 12, Bruno et al. disclose the access line is a wordline ["...to a word line." – claim 1 (The final destination of the switched connection is the word line (which is the access line).)].
With respect to claim 13, Bruno et al. disclose a wordline decoder ["Address decoder (WLDEC2) for selectively applying to the word lines (WLi, j)..." – claim 1 (the patent explicitly names an address decoder specifically dedicated to driving and selecting word lines (WLDEC2), which matches the target term directly.)] coupled to the first and second voltage supplies ["...delivering word group selection signals (GPi) of word lines which are of variable polarity (VPOS, VNEG)..." – claim 1 ( For the group decoder (GPGEN) to deliver signals that inherit or pass through the variable polarities (VPOS) and (VNEG), the internal multiplexing components (TP1, TP2, TN1, TN2) must be electrically connected or coupled to those respective positive and negative voltage sources.)].
With respect to claim 14, Bruno et al. disclose the wordline decoder is configured to ["Address decoder (WLDEC2) for selectively applying to the word lines (WLi, j) of a memory plane (MA)..." – claim 1] select a wordline ["...to select and selectively apply one of these signals to a word line." – claim 1] for accessing a memory cell ["...to the word lines (WLi, j) of a memory plane (MA)..." – claim 1].
With respect to claim 15, Bruno et al. disclose a digit line decoder used to access the memory cell [SECTO-SECT5 of fig 3a].
Claim(s) 17-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KYU et al. [KR 20150099093 A].
With respect to claim 17, KYU discloses a method comprising [12th par. of the DESCRIPTION-OF EMBODIMENTS]: accessing a memory cell during a write operation ["...when the voltage is increased at both ends of the memory cell in the first limiting current I1 state... when the memory cell is programmed in the Set state..." (in both, the application and patent, the objective is to put the memory cell into a programmed state (a write/Set operation))], wherein the accessing comprises selecting a voltage based on a polarity "...the voltage of the opposite polarity will be applied." (both, the application and patent, using electrical polarity as a parameter to apply or program the memory cell.)]; and after accessing the memory cell, limiting a current through the memory cell "...the first limiting current I1 will be kept constant despite the increase of the voltage applied..." and "...maintained at the second limit current I2 level..." (both, the application and patent, establish a current limit during a time frame after a first time frame – the patent has a second limit during a second time frame.)].
With respect to claim 18, KYU discloses the polarity is a program polarity [Reference A supports Phrase C by explicitly associating the polarity with a programming ("Set") state. – see 12th par. of the DESCRIPTION-OF EMBODIMENTS].
With respect to claim 19, KYU discloses accessing the memory cell comprises applying the voltage to a wordline [the variable resistance memory cell includes a bit line BL and a variable resistance element R connected to the word line WL. In the write operation to the variable resistance memory cell of FIG. 2, data writing can be performed by the voltage applied between the bit line BL and the word line WL instead of the selection element – see 6th par. of the DESCRIPTION-OF EMBODIMENTS].
Allowable Subject Matter
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 4: The device of claim 1, wherein the voltage is applied to access a memory cell, current passes through first circuitry when operating in a first program polarity, and the current passes through second circuitry when operating in a second program polarity.
With respect to claim 6: The device of claim 1, wherein the wordline is used to sense a current to determine a logic state of a memory cell.
-with respect to claim 7: The device of claim 1, wherein a memory cell snaps after being accessed using the wordline during a read or write operation.
-with respect to claim 16: (Original) The apparatus of claim 15, wherein the digit line decoder is coupled to the first and second voltage supplies.
-with respect to claim 20: The method of claim 17, further comprising sensing the current.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 June 7, 2026
Prosecution Insights