DETAILED ACTION
The Applicant Arguments/Remarks filed January 23, 2026 has been entered. Claims 1-10 are pending. Claims 1, 4 and 8 are independent.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morley (US 5,774,080).
Regarding claims 1-10, the claimed limitation(s) of parallel latches (including D-type flip-flops) with alternating divide by 2 clocking is a well-known technology for a type of data system for its purpose.
For support, of the above asserted facts, see for example, Morley, FIGS. 4-12 and accompanying disclosure, including data path logic array consists of address, ram, etc. described in background of the invention.
Further, see other examples, Hargis et al. (US 2002/0172079), FIG. 5; JP-2009077058, FIG. 1 and accompanying disclosure, with combination of double clocking in FIG. 5 of Foley et al. (US 6,696,995).
Response to Argument
Applicant’s arguments filed 01/23/2026, with respect to the rejection(s) of claims under 35 USC 102, have been fully considered but are not persuasive.
The claimed limitation(s) of parallel latches (including D-type flip-flops) with alternating divide by 2 clocking is a well-known technology for a type of data system for its purpose. The prior art cited in the aforementioned art rejection reads on all the element of the claimed limitations.
The following concerns independent claim 1, a prior art of Morley teaches a device (see e.g., FIG. 4) comprising:
a first latch (see EXMINER’S MARKUP below) configured to receive data (In) and a half-clock signal (CLOCK/2);
a second latch in parallel with the first latch, the second latch (see EXAMINER’S MARKUP below) configured to receive the data (In) and an inverted half-clock signal (/Clock/2); and
an output circuit (see EXMINER’S MARKUP below) connected to data outputs of the first and second latches, the output circuit to provide the data alternately from the first latch and the second latch according to the half-clock signal (see FIGS. 4-5 and accompanying disclosure).
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Morley discloses all other claimed limitations. Further, see other references, Hargis et al. (US 2002/0172079), JP-2009077058, and Foley et al. (US 6,696,995).
Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/ Primary Examiner, Art Unit 2825