CTNF 18/679,058 CTNF 79224 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This office action is in response to the application filed on 5/30/24. Claims 1-20 are pending. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement 06-52 The information disclosure statements (IDS) were submitted on 5/30/24 and 4/02/25. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification 06-31 AIA The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-6, 8-12, 17, 19 and 20 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Choi et al. (US PGPub 2022/0328586, hereinafter referred to as “Choi”) . Choi discloses the semiconductor display device as claimed. See figures 1-11 and corresponding text, where Choi teaches, claim 1 , a display apparatus, comprising: a substrate (100) including a display area (DA) and a non-display area ( NDA) adjacent to the display area (DA) (figures 1-3; [0064]); a pixel (P) disposed in the display area (DA) of the substrate (100) , the pixel (P) including at least one transistor (130) and a light emitting diode (220) (figure 4; [0083], [0095]) a touch sensor unit (711, 713) disposed on the pixel (P) , the touch sensor unit (711, 713) including at least one touch electrode (TD) (figure 6; [0141-0146]); a common power line (40) disposed in the non-display area (NDA) of the substrate (100) and electrically connected to the light emitting diode (220) (figure 1; [0065-0071]; and a gate driving circuit (13) disposed in the non-display area (NDA) of the substrate (100) , wherein the common power line (40) and the gate driving circuit overlap (13) each other in at least a part of the non-display area (NDA) (figure 1; [0068-0070], the examiner views that since the common power line (40) connects to the driving circuit by crossing to the physical connection to the pads (24) both the common power line (40) and the gate driving circuit (13) overlap with each other ). Choi teaches, claim 2 , wherein the non-display area includes: a first non-display area (right side) disposed at a first edge of the substrate (100) ; a second non-display area (left side) disposed at a second edge of the substrate (100) opposing the first non-display area; a third non-display area ( bottom edge) disposed at a third edge of the substrate; and a fourth non-display area disposed at a fourth edge of the substrate opposing the third non-display area (figures 1-3; [0064-0074]). Choi teaches, claim 3 , wherein the gate driving circuit (13) is disposed in the third non-display area ( bottom edge) and the fourth non-display area (portion above and opposite the bottom edge) , wherein the common power line (40) is disposed in a part of the first non-display area and in the second to fourth non-display areas, and wherein the gate driving circuit and the common power line overlap each other in at least one of the third non-display area and the fourth non-display area (figures 1-3; [0064-0074]). Choi teaches, claim 4 , wherein the touch sensor unit includes: a touch electrode part (TSL) including at least one touch electrode (711, 713) ; a first routing part including a first routing line disposed in a part of the first non-display area and in the second to fourth non-display areas; and a second routing part including a second routing line disposed in a part of the first non-display area and in the second to fourth non-display areas, wherein the second routing line overlaps the common power line from a plan view (figure 6; [0141-0146]). Choi teaches, claim 5 , wherein the gate driving circuit and the second routing line overlap each other in at least one of the third non-display area and the fourth non-display area (figures 1-3; [0064-0074]). Choi teaches, claim 6 , wherein the second routing line is disposed outside the first routing line. Choi teaches, claim 8 , further comprising: a pad part disposed in the first non-display area, wherein the common power line is electrically connected to the pad part to receive a common power voltage (figures 1-3; [0064-0074]). Choi teaches, claim 9 , wherein the gate driving circuit is disposed on the same layer as the at least one transistor. Choi teaches, claim 10 , further comprising: a planarization layer disposed on the at least one transistor; an interlayer insulating layer disposed on the planarization layer; and a bank layer disposed on the interlayer insulating layer and defining a pixel area of the pixel and an opening area inside the pixel area, wherein the light emitting diode includes: a first electrode disposed on the interlayer insulating layer and electrically connected to the at least one transistor through a first contact hole penetrating through the interlayer insulating layer and the planarization layer; an emission layer disposed on the first electrode and being in contact with the first electrode in the opening area; and a second electrode disposed on the emission layer. Choi teaches, claim 11 , further comprising: a common power connection line disposed on the interlayer insulating layer in the non-display area, wherein the second electrode is in contact with the common power connection line through a second contact hole penetrating through the bank layer in the non-display area. Choi teaches, claim 12 , wherein the common power connection line is in contact with the common power line through a third contact hole penetrating through the interlayer insulating layer in the third non-display area and the fourth non-display area. Choi teaches, claim 17 , wherein the gate driving circuit is disposed in the third non-display area and the fourth non-display area, wherein the common power line is disposed in a part of the first non-display area and in the third and fourth non-display areas, and wherein the gate driving circuit and the common power line overlap each other in at least one of the third non-display area and the fourth non-display area (figures 1-3; [0064-0074]). Choi teaches, claim 19 , wherein the common power connection line is disposed to overlap at least a part of the gate driving circuit and the common power line from a plan view (figures 1-3; [0064-0074]). Choi teaches, claim 20 , wherein the common power connection line is disposed in the third non-display area and the fourth non-display area to overlap the gate driving circuit and the common power line from a plan view (figures 1-3; [0064-0074]) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 7, 13-16 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STANETTA D ISAAC/Examiner, Art Unit 2898 June 11, 2026 Application/Control Number: 18/679,058 Page 2 Art Unit: 2898 Application/Control Number: 18/679,058 Page 3 Art Unit: 2898 Application/Control Number: 18/679,058 Page 4 Art Unit: 2898 Application/Control Number: 18/679,058 Page 5 Art Unit: 2898 Application/Control Number: 18/679,058 Page 6 Art Unit: 2898 Application/Control Number: 18/679,058 Page 7 Art Unit: 2898 Application/Control Number: 18/679,058 Page 8 Art Unit: 2898
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