DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-21 are objected to because of the following informalities:
Claim 1 recites “the plurality of conductive layers comprise” (line 10) which should be replaced with “the plurality of conductive layers comprises” to improve claim language.
Claim 1 recites “the plurality of gate contact plugs comprise” (line 15) which should be replaced with “the plurality of gate contact plugs comprises” to improve claim language.
Claim 12 recites “the plurality of conductive layers comprise” (line 10) which should be replaced with “the plurality of conductive layers comprises” to improve claim language.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-7, 9, 11-15, and 18-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0139831 to Kim et al. (hereinafter Kim).
With respect to claim 1, Kim discloses a semiconductor memory device (e.g., see the annotated Figs. 3A and 9 below) (Kim, Figs. 1A, 3A, 9, 10B, ¶0002-¶0008, ¶0034-¶0066, ¶0133-¶0157), comprising:
a gate stacked body (ST) (Kim, Figs. 1A, 3A, 9, 10B, ¶0034-¶0036, ¶0047-¶0048) including a cell array area (MCA) and a contact area (SA) extending from the cell array area (MCA) in a first direction (e.g., X-direction), and including a plurality of conductive layers (115g) and a plurality of interlayer insulating layers (38/47 and 62/75) that are alternately stacked in a second direction (e.g., Z direction) intersecting a plane extending in the first direction (X); and
a plurality of gate contact plugs (136) (Kim, Figs. 1A, 3A, 9, 10B, ¶0034, ¶0057-¶0066, ¶0133-¶0157) penetrating the plurality of conductive layers (115g) and the plurality of interlayer insulating layers (38/47 and 62/75) in the contact area (SA),
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wherein the plurality of conductive layers (115g) (Kim, Figs. 1A, 3A, 9, 10B, ¶0047-¶0048, ¶0064) comprise a plurality of first conductive layers (115L) arranged in the second direction (Z) to form a first sub-stacked body (LS’) and a plurality of second conductive layers (115U) arranged over the first sub-stacked body (LS’) in the second direction (Z) to form a second sub-stacked body (US’),
wherein the plurality of gate contact plugs (136) comprise a first gate contact plug (136_1, on the left side of Fig. 3A) (Kim, Figs. 1A, 3A, 9, 10B, ¶0058-¶0066) contacting a corresponding second conductive layer (e.g., the most upper layer 115U) among the plurality of second conductive layers (115U),
wherein the first gate contact plug (136_1) comprises a first portion (e.g., 136L) (Kim, Figs. 9, 10B, ¶0063-¶0064, ¶0134, ¶0145-¶0146) penetrating the first sub-stacked body (LS’), a first contact portion (136E1) spaced apart from the first portion (136L) in the second direction (Z) and contacting the corresponding second conductive layer (115U) (Kim, Figs. 9, 10B, ¶0145-¶0146), and a second portion (e.g., 136U1, under the first contact portion 136E1) extending from the first portion (136L) toward the first contact portion (136E1) to contact the first contact portion (136E1), and
wherein the second portion (e.g., 136U1, under the first contact portion 136E1) (Kim, Figs. 9, 10B, ¶0145-¶0146) in the first direction (X) is narrower than the first contact portion (136E1).
Regarding claim 2, Kim discloses the semiconductor memory device according to claim 1. Further, Kim discloses the semiconductor memory device, wherein the second portion (e.g., 136U1, under the first contact portion 136E1) (Kim, Figs. 9, 10B, ¶0134, ¶0145-¶0146) in the first direction is narrower than the first portion (136L).
Regarding claim 3, Kim discloses the semiconductor memory device according to claim 1. Further, Kim discloses the semiconductor memory device, wherein: the first contact portion (136E1) (Kim, Figs. 9, 10B, ¶0145) of the first gate contact plug (136_1) comprises a first protrusion (136P, on the left side) protruding toward the second conductive layer (115U) in a negative first direction (-X) to form a first contact surface with the second conductive layer (115U), and the first contact portion (136E1) of the first gate contact plug comprises a second protrusion (136P, on the right side) protruding toward the second conductive layer (115U) in a positive first direction (+X) to form another first contact surface with the second conductive layer (115U).
Regarding claim 4, Kim discloses the semiconductor memory device according to claim 1. Further, Kim discloses the semiconductor memory device, further comprising: a sidewall insulating structure (62/75) (Kim, Figs. 9, 10B, ¶0048-¶0049, ¶0052-¶0053, ¶0136) extending along a sidewall of the first gate contact plug (136_1), wherein the sidewall insulating structure (62/75) comprises a first sidewall insulation pattern (75, an insulating pattern over 136E1) and a second sidewall insulation pattern (e.g., the most upper insulating pattern 62 under 136E1) that are spaced apart from each other by a contact surface (e.g., a contact surface between 136E1 and 115U) between the first contact portion (136E1) of the first gate contact plug and the corresponding second conductive layer (115U).
Regarding claim 6, Kim discloses the semiconductor memory device according to claim 1. Further, Kim discloses the semiconductor memory device, wherein: the contact area (SA) comprises a first contact area (e.g., including gate contact plugs 136_1) (Kim, Figs. 1A, 3A, ¶0058, ¶0062-¶0066, ¶0134) and a second contact area (e.g., including gate contact plugs 136_2) that are adjacent to each other, the plurality of gate contact plugs comprise the first gate contact plug (e.g., the gate contact plugs 136_1) disposed in the first contact area and a second gate contact plug (e.g., the gate contact plugs 136_2) disposed in the second contact area, and the second gate contact plug (e.g., the gate contact plugs 136_2) contacts a corresponding first conductive layer (115L) among the plurality of first conductive layers.
Regarding claim 7, Kim discloses the semiconductor memory device according to claim 6. Further, Kim discloses the semiconductor memory device, wherein: the second gate contact plug (136_2) (Kim, Figs. 1A, 3A, ¶0058, ¶0062-¶0066, ¶0134) comprises a second contact portion (136E) extending from the corresponding first conductive layer (115L) in the second direction (Z) to penetrate the second sub-stacked body (US’), and an extension portion (136L, under 136E of the second gate contact plug 136_2) extending from the second contact portion (136E) in a third direction (-Z) opposite to the second direction (+Z), and the extension portion (136L) in the first direction (X) is narrower than the second contact portion (136E).
Regarding claim 9, Kim discloses the semiconductor memory device according to claim 7. Further, Kim discloses the semiconductor memory device, further comprising: a sidewall insulating structure (47/38) (Kim, Figs. 9, 10B, ¶0048-¶0049, ¶0053, ¶0058, ¶0063) extending along a sidewall of the second gate contact plug (136_2), wherein the sidewall insulating structure (47/38) comprises a first sidewall insulation pattern (47, an insulating pattern over 136E) and a second sidewall insulation pattern (e.g., the most upper insulating pattern 38 under 136E) that are spaced apart from each other by a contact surface (e.g., a contact surface between 136E and 115L) between the second contact portion (136E) of the second gate contact plug and the corresponding first conductive layer (115L).
Regarding claim 11, Kim discloses the semiconductor memory device according to claim 1. Further, Kim discloses the semiconductor memory device, further comprising: a channel layer (e.g., memory vertical structure 81 including a channel layer 85) (Kim, Figs. 1A, 3A, 4, ¶0092-¶0103) penetrating the plurality of conductive layers (115g) and the plurality of interlayer insulating layers (38/48 and 62/75) in the cell array area (MCA); and a memory layer (83) provided between the channel layer (85) and the gate stacked body (ST).
With respect to claim 12, Kim discloses a semiconductor memory device (e.g., see the annotated Figs. 3A and 9 above) (Kim, Figs. 1A, 3A, 9, 10B, ¶0002-¶0008, ¶0034-¶0066, ¶0133-¶0157), comprising:
a gate stacked body (ST) (Kim, Figs. 1A, 3A, 9, 10B, ¶0034-¶0036, ¶0047-¶0048) including a cell array area (MCA) and a contact area (SA) extending from the cell array area (MCA) in a first direction (e.g., X-direction), and including a plurality of conductive layers (115g) and a plurality of interlayer insulating layers (38/47 and 62/75) that are alternately stacked in a second direction (e.g., Z direction) intersecting a plane extending in the first direction (X); and
a first sub-contact set comprising a plurality of first gate contact plugs (136) (Kim, Figs. 1A, 3A, 9, 10B, ¶0034, ¶0057-¶0066, ¶0133-¶0157) penetrating the plurality of conductive layers (115g) and the plurality of interlayer insulating layers (38/47 and 62/75) in the contact area (SA),
wherein the plurality of conductive layers (115g) (Kim, Figs. 1A, 3A, 9, 10B, ¶0047-¶0048, ¶0064) comprise a plurality of first conductive layers (115L) arranged in the second direction (Z) to form a first sub-stacked body (LS’) and a plurality of second conductive layers (115U) arranged over the first sub-stacked body (LS’) in the second direction (Z) to form a second sub-stacked body (US’) and contact the plurality of first gate contact plugs (136), respectively,
wherein the first sub-contact set comprises a plurality of first portions (136L) (Kim, Figs. 3A, 9, 10B, ¶0063-¶0064, ¶0134, ¶0145-¶0146) penetrating the first sub-stacked body (LS’) and forming lower portions of the plurality of first gate contact plugs (136), a plurality of first contact portions (136E) forming upper portions of the plurality of first gate contact plugs, and a plurality of second portions (136U, under the contact portions 136E) forming middle portions of the plurality of first gate contact plugs, and
wherein a sidewall of each of the plurality of first gate contact plugs (136) comprises a groove (e.g., between the contact portion 136E1 and the lower portion 136L) (Kim, Fig. 9, ¶0134, ¶0145-¶0146) defined between a corresponding first contact portion among the plurality of first contact portions (136E) and a corresponding first portion among the plurality of first portions (136L).
Regarding claim 13, Kim discloses the semiconductor memory device according to claim 12. Further, Kim discloses the semiconductor memory device, wherein the plurality of first contact portions (136E1) (Kim, Figs. 3A, 9, 10B, ¶0063-¶0064, ¶0134, ¶0145-¶0146) contact the plurality of second conductive layers (115U), respectively.
Regarding claim 14, Kim discloses the semiconductor memory device according to claim 12. Further, Kim discloses the semiconductor memory device, wherein the plurality of first portions (e.g., 136L of the gate contact plugs 136_1) (Kim, Figs. 3A, 9, 10B, ¶0063-¶0064, ¶0134, ¶0145-¶0146) are formed to have the substantially same length along the second direction (Z).
Regarding claim 15, Kim discloses the semiconductor memory device according to claim 12. Further, Kim discloses the semiconductor memory device, wherein the plurality of second portions (e.g., 136U1, under the gate contact portions 136E1) (Kim, Figs. 3A, 9, 10B, ¶0063-¶0064, ¶0134, ¶0145-¶0146) are formed to have different lengths along the second direction (Z).
Regarding claim 18, Kim discloses the semiconductor memory device according to claim 12. Further, Kim discloses the semiconductor memory device, further comprising: a second sub-contact set including a plurality of second gate contact plugs (136_2) (Kim, Figs. 1A, 3A, ¶0058, ¶0062-¶0066, ¶0134) that penetrate the plurality of conductive layers (155g) and the plurality of interlayer insulating layers (38/47 and 62/75) in the contact area (SA), wherein the second sub-contact set (136_2) comprises a plurality of second contact portions (136E and 136U above 136E) forming upper portions of the plurality of second gate contact plugs and a plurality of extension portions (136L) forming lower portions of the plurality of second gate contact plugs, and wherein each of the plurality of second contact portions (136E) comprises a contact surface contacting a corresponding first conductive layer (115L) among the plurality of first conductive layers, and extends from the contact surface in the second direction (Z) to penetrate the second sub-stacked body (US’).
Regarding claim 19, Kim discloses the semiconductor memory device according to claim 18. Further, Kim discloses the semiconductor memory device, wherein: each of the plurality of extension portions (136L) (Kim, Figs. 1A, 3A, ¶0058, ¶0062-¶0066, ¶0134) extends from a corresponding second contact portion (136E) among the plurality of second contact portions in a third direction (-Z) opposite to the second direction (+Z), and each of the plurality of extension portions (136L) in the first direction (X) is narrower than each of the plurality of second contact portions (136E).
Regarding claim 20, Kim discloses the semiconductor memory device according to claim 18. Further, Kim discloses the semiconductor memory device, further comprising: a first sidewall insulating pattern (75) (Kim, Figs. 9, 10B, ¶0048-¶0049, ¶0052-¶0053, ¶0136) enclosing a sidewall of each of the plurality of second contact portions (136E/136U); and a second sidewall insulation pattern (109a) (Kim, Figs. 9, 10B, ¶0146) enclosing a sidewall of each of the plurality of extension portions (136L), wherein the first sidewall insulation pattern (75) and the second sidewall insulation pattern (109a) are spaced apart from each other by the contact surface (e.g., between 136E and the first conductive layer 115L).
Regarding claim 21, Kim discloses the semiconductor memory device according to claim 18. Further, Kim discloses the semiconductor memory device, wherein a length of the plurality of second portions (e.g., 136U, under the contact 136E1 of the first gate contact plugs 136_1) (Kim, Figs. 3A, 9, 10B, ¶0058, ¶0063-¶0064, ¶0134, ¶0145-¶0146) in the second direction (Z) is proportional (e.g., the length of each of the second portions 136U under the contact portion 136E1 of the plurality of first gate contact plugs 136_1 increases with increasing distance from the plurality of second gate contact plugs 136_2) to a separation distance from the second sub-contact set (e.g., plurality of second gate contact plugs 136_2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 10, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0139831 to Kim in view of Mushiga et al. (US 2019/0252396, hereinafter Mushiga).
Regarding claim 5, Kim discloses the semiconductor memory device according to claim 4. Further, Kim does not specifically disclose the semiconductor memory device, wherein: the first sidewall insulation pattern encloses an upper sidewall of the first contact portion protruding beyond the contact surface in the second direction, and the second sidewall insulation pattern encloses a sidewall of the first portion, and extends onto a sidewall of the second portion.
However, Mushiga teaches forming a plurality of gate contact plugs (e.g., column-shaped conductive via structure 86C) (Mushiga, Figs. 28A-28C, ¶0002, ¶0004-¶0007, ¶0193, ¶0195, ¶0197-¶0201) having a Doric column (Mushiga, Fig. 28C, ¶0193, ¶0198) and comprising a first contact portion (86P) (Mushiga, Fig. 28C, ¶0198), a first portion (86S/86B) penetrating the first sub-stacked body (132/146), and a second portion (86S) penetrating the second sub-stacked body (232/246), a first sidewall insulation pattern (844) (Mushiga, Fig. 28C, ¶0195, ¶0201) and a second sidewall insulation pattern (842) that are spaced apart from each other by a contact surface (e.g., a surface-to-surface contact between the contact portion 86P and the topmost conductive layer 246) (Mushiga, Fig. 28C, ¶0201) between the first contact portion (86P) of the first gate contact plug (86C) and the corresponding second conductive layer (e.g., the topmost conductive layer 246), wherein: the first sidewall insulation pattern (e.g., a cylindrical portion 844) encloses an upper sidewall of the first contact portion (86P) protruding beyond the contact surface in the second direction (e.g., vertical direction in Fig. 28C), and the second sidewall insulation pattern (e.g., a neck portion 84N) encloses a sidewall of the first portion (86S/86B) penetrating the first sub-stacked body (132/146), and extends onto a sidewall of the second portion (86S) penetrating the second sub-stacked body (232/246), to improve connections between the gate via structures and the respective gate layers to provide improved three-dimensional memory device including through memory-level contact via structures.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Kim by forming conformal dielectric via liner including a cylindrical portion as a first sidewall insulation pattern and a neck portion as a second sidewall insulation pattern as taught by Mushiga to have the semiconductor memory device, wherein: the first sidewall insulation pattern encloses an upper sidewall of the first contact portion protruding beyond the contact surface in the second direction, and the second sidewall insulation pattern encloses a sidewall of the first portion, and extends onto a sidewall of the second portion, in order to provide improved connections between the gate via structures and the respective gate layers to provide improved three-dimensional memory device including through memory-level contact via structures (Mushiga, ¶0002, ¶0004-¶0007, ¶0193, ¶0195, ¶0198-¶0201).
Regarding claim 10, Kim discloses the semiconductor memory device according to claim 9. Further, Kim does not specifically disclose the semiconductor memory device, wherein: the first sidewall insulation pattern encloses an upper sidewall of the second contact portion extending from the contact surface in the second direction, and the second sidewall insulation pattern encloses a sidewall of the extension portion.
However, Mushiga teaches forming a plurality of gate contact plugs (e.g., column-shaped conductive via structure 86C) (Mushiga, Figs. 28A-28C, ¶0002, ¶0004-¶0007, ¶0193, ¶0195, ¶0197-¶0201) having a Doric column (Mushiga, Fig. 28C, ¶0193, ¶0198) and comprising a first contact portion (86P) (Mushiga, Fig. 28C, ¶0198), a first portion (86S/86B) penetrating the first sub-stacked body (132/146), and a second portion (86S) penetrating the second sub-stacked body (232/246), a first sidewall insulation pattern (844) (Mushiga, Fig. 28C, ¶0195, ¶0201) and a second sidewall insulation pattern (842) that are spaced apart from each other by a contact surface (e.g., a surface-to-surface contact between the contact portion 86P and the topmost conductive layer 246) (Mushiga, Fig. 28C, ¶0201) between the first contact portion (86P) of the first gate contact plug (86C) and the corresponding second conductive layer (e.g., the topmost conductive layer 246), wherein: the first sidewall insulation pattern (e.g., a cylindrical portion 844) encloses an upper sidewall of the second contact portion (86P) extending from the contact surface in the second direction (e.g., vertical direction in Fig. 28C), and the second sidewall insulation pattern (e.g., a neck portion 84N) encloses a sidewall of the extension portion (86S) penetrating the first sub-stacked body (132/146), to improve connections between the gate via structures and the respective gate layers to provide improved three-dimensional memory device including through memory-level contact via structures.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Kim by forming conformal dielectric via liner including a cylindrical portion as a first sidewall insulation pattern and a neck portion as a second sidewall insulation pattern as taught by Mushiga to have the semiconductor memory device, wherein: the first sidewall insulation pattern encloses an upper sidewall of the second contact portion extending from the contact surface in the second direction, and the second sidewall insulation pattern encloses a sidewall of the extension portion in order to provide improved connections between the gate via structures and the respective gate layers to provide improved three-dimensional memory device including through memory-level contact via structures (Mushiga, ¶0002, ¶0004-¶0007, ¶0193, ¶0195, ¶0198-¶0201).
Regarding claim 16, Kim discloses the semiconductor memory device according to claim 12. Further, Kim does not specifically disclose the semiconductor memory device, further comprising: a first sidewall insulation pattern enclosing a sidewall of each of the plurality of first contact portions, and a second sidewall insulation pattern enclosing a sidewall of each of the plurality of first portions, and extending onto a sidewall of each of the plurality of second portions.
However, Mushiga teaches forming a plurality of gate contact plugs (e.g., column-shaped conductive via structure 86C) (Mushiga, Figs. 28A-28C, ¶0002, ¶0004-¶0007, ¶0193, ¶0195, ¶0197-¶0201) having a Doric column (Mushiga, Fig. 28C, ¶0193, ¶0198) and each comprising a first contact portion (86P) (Mushiga, Fig. 28C, ¶0198), a first portion (86S/86B) penetrating the first sub-stacked body (132/146), and a second portion (86S) penetrating the second sub-stacked body (232/246), a first sidewall insulation pattern (844) (Mushiga, Fig. 28C, ¶0195, ¶0201) and a second sidewall insulation pattern (842) that are spaced apart from each other by a contact surface (e.g., a surface-to-surface contact between the contact portion 86P and the topmost conductive layer 246) (Mushiga, Fig. 28C, ¶0201) between the first contact portion (86P) of the first gate contact plug (86C) and the corresponding second conductive layer (e.g., the topmost conductive layer 246), wherein: the first sidewall insulation pattern (e.g., a cylindrical portion 844) encloses an upper sidewall of the first contact portion (86P) protruding beyond the contact surface in the second direction (e.g., vertical direction in Fig. 28C), and the second sidewall insulation pattern (e.g., a neck portion 84N) encloses a sidewall of the first portion (86S/86B) penetrating the first sub-stacked body (132/146), and extends onto a sidewall of the second portion (86S) penetrating the second sub-stacked body (232/246), to improve connections between the gate via structures and the respective gate layers to provide improved three-dimensional memory device including through memory-level contact via structures.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Kim by forming conformal dielectric via liner including a cylindrical portion as a first sidewall insulation pattern and a neck portion as a second sidewall insulation pattern as taught by Mushiga to have the semiconductor memory device, further comprising: a first sidewall insulation pattern enclosing a sidewall of each of the plurality of first contact portions, and a second sidewall insulation pattern enclosing a sidewall of each of the plurality of first portions, and extending onto a sidewall of each of the plurality of second portions, in order to provide improved connections between the gate via structures and the respective gate layers to provide improved three-dimensional memory device including through memory-level contact via structures (Mushiga, ¶0002, ¶0004-¶0007, ¶0193, ¶0195, ¶0198-¶0201).
Regarding claim 17, Kim in view of Mushiga discloses the semiconductor memory device according to claim 16. Further, Kim discloses the semiconductor memory device, wherein: each of the plurality of first contact portions (136E1) (Kim, Figs. 9, 10B, ¶0145) comprises a contact surface (e.g., a surface between the protrusion 136P and the conductive layer 115U) contacting a corresponding second conductive layer (115U) among the plurality of second conductive layers, but does not specifically disclose that the first sidewall insulation pattern and the second sidewall insulation pattern are spaced apart from each other by the contact surface.
However, Mushiga teaches the first sidewall insulation pattern (844) (Mushiga, Fig. 28C, ¶0195, ¶0201) and the second sidewall insulation pattern (842) that are spaced apart from each other by the contact surface (e.g., a surface-to-surface contact between the contact portion 86P and the topmost conductive layer 246) (Mushiga, Fig. 28C, ¶0201).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Kim/Mushiga by forming a conformal dielectric via liner including a cylindrical portion as a first sidewall insulation pattern and a neck portion as a second sidewall insulation pattern as taught by Mushiga to have the semiconductor memory device, wherein: the first sidewall insulation pattern and the second sidewall insulation pattern are spaced apart from each other by the contact surface, in order to provide improved connections between the gate via structures and the respective gate layers to provide improved three-dimensional memory device including through memory-level contact via structures (Mushiga, ¶0002, ¶0004-¶0007, ¶0193, ¶0195, ¶0198-¶0201).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0139831 to Kim.
Regarding claim 8, Kim discloses the semiconductor memory device according to claim 7. Further, Kim does not specifically disclose discloses the semiconductor memory device, wherein: the second contact portion of the second gate contact plug comprises a first protrusion protruding toward the first conductive layer in a negative first direction to form a second contact surface with the first conductive layer, and the second contact portion of the second gate contact plug comprises a second protrusion protruding toward the first conductive layer in a positive first direction to form another second contact surface with the first conductive layer.
However, Kim teaches forming the first contact portion (136E1) (Kim, Figs. 9, 10B, ¶0145) of the first gate contact plug (136_1) that comprises a first protrusion (136P, on the left side) protruding toward the second conductive layer (115U) in a negative first direction (-X) to form a first contact surface with the second conductive layer (115U), and the first contact portion (136E1) of the first gate contact plug comprises a second protrusion (136P, on the right side) protruding toward the second conductive layer (115U) in a positive first direction (+X) to form another first contact surface with the second conductive layer (115U), to improve connections between the first contact portion (136E1) and corresponding topmost second conductive layer (115U).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Kim by forming the second contact portion including a first protrusion as the first protrusion of the first contact portion of the first gate contact plug of Kim to have the semiconductor memory device, wherein: the second contact portion of the second gate contact plug comprises a first protrusion protruding toward the first conductive layer in a negative first direction to form a second contact surface with the first conductive layer, and the second contact portion of the second gate contact plug comprises a second protrusion protruding toward the first conductive layer in a positive first direction to form another second contact surface with the first conductive layer, in order to improve connections between the first contact portion and corresponding topmost second conductive layer, and thus to obtain a three-dimensional semiconductor device with improved integration density and reliability (Kim, ¶0004, ¶0145).
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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