DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d).
Information Disclosure Statement
The information disclosure statement filed on 1/15/2025 has been acknowledged and a signed copy of the PTO-1449 is attached herein.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "the unique code" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "the unique code" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagatomo et al. (USPN 9480144 B2, hereinafter “Nagatomo”).
In regards to claim 1, Nagatomo discloses (see, for example, Fig. 1) a heat dissipation substrate (10) for a power semiconductor module (1), comprising:
a first metal plate (12);
an insulating substrate (11) bonded to the first metal plate (12); and
a second metal plate (13) bonded on the insulating substrate (11),
wherein a first thickness (t1 ) of the first metal plate (12) is different from a second thickness (t2 ) of the second metal plate (13).
In regards to claim 2, Nagatomo discloses (See, for example, Fig. 1) that wherein the first thickness (t1 ) of the first metal plate (12) is thinner than the second thickness (t2 ) of the second metal plate (13).
In regards to claim 9, Nagamoto discloses (see, for example, Fig. 1) a heat dissipation substrate (10) for a power semiconductor module (1), comprising:
a second metal plate (12);
an insulating substrate (11) bonded to the second metal plate (12); and
a third metal plate (13) bonded on the insulating substrate (11),
wherein a third thickness (t2 ) of the third metal plate (13) is thicker than a second
thickness (t1 ) of the second metal plate (12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 4, 5 an 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over
Nagatomo in view of Phan et al. (USPN 7100826 B1, hereinafter “Phan”).
In regards to claims 3, Nagatomo discloses (See, for example, Fig. 1) wherein the first metal plate (12) comprises a circuit pattern electrically connected to a power semiconductor device (See, for example, “circuit layer”, Abstract).
However, Nagatomo is silent about the second metal plate comprises a marked first unique code.
Phan while disclosing a semiconductor wafer marking teaches (see, for example, Figs. 3, 6 and 11) the second metal plate comprises a marked first unique code (“The barcode data store 610 can store information including, but not limited to, data for interpreting barcodes, data for mapping barcode codes to wafer information, rules for interpreting barcodes and processing status of one or more wafers. The barcode data store 610 thus facilitates improving integrated circuit manufacturing by providing data concerning
wafers in one or more phases of integrated circuit manufacture.”, See Col. 10 lines 20-31;
“The barcode reader 330 can pass a wafer, and/or information concerning a wafer…
distinguishing between wafers based on supplier, distinguishing between wafers based on
materials in the wafer and distinguishing between wafers based on stages of processing
through which a wafer has passed. By way of illustration, wafers of a first thickness can be
routed to a first destination by the sorter 340 while wafers of a second thickness can be
routed to a second destination.”, See Col. 7 lines10-26).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to incorporate the mark of Phan on the second metal layer of
the Nagamoto substrate because this would help identify and history for the traceability purposes; and ensures efficient integrated circuit manufacturing.
In regards to claim 4, Nagamoto as modified above discloses (See, for example, Figs. 3, 6 and 11, Phan) that wherein the first unique code comprises thickness information of the insulating substrate (See, for example, Col. 7 lines 10-26).
In regards to claim 5, Nagamoto as modified above discloses (See, for example, Figs. 3, 6 and 11, Phan) that wherein the first unique code comprises thickness information of at least one of
the first metal plate and the second metal plate( “…The wafer 100 is marked with a barcode 110…The bar code 110 can encode information include, but not limited to, …conditions
under which the wafer 100 was produced and properties of the manufactured wafer. The properties of the manufactured wafer 100 can include ….thickness…”, See Col. 5 lines 21-
39; See also Col. 7 lines 10-26).
In regards to claims 11 and 12, Nagamoto discloses all limitations of claim 9 above except that
wherein the unique code comprises thickness information of the insulating substrate (claim 11); and wherein the unique code comprises thickness information of at least one of the first and
second metal plates (claim 12).
Phan discloses (See, for example, Figs. 3, 6 and 11) that wherein the unique code comprises
thickness information of the insulating substrate (See, for example, Col. 7 lines 10-26); and
wherein the unique code comprises thickness information of at least one of the first and second
metal plates (See, for example, Claims 26-29).
Therefore, it would have been obvious to one having ordinary skill in the art before the
effective filing date of the invention to incorporate the mark of Phan on the second metal layer of
the Nagamoto substrate because this would help identify and history for the traceability
purposes; and ensures efficient integrated circuit manufacturing.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Nagatomo in
view of Phan as applied to claim 3 above, and further in view of Yoshida et al. (USPN
7679202 B2, hereinafter “Yoshida”).
In regards to claim 6, Nagamoto as modified above discloses (See, for example, Fig. 1) the insulating substrate (11).
Nagamoto as modified above further fails to explicitly teach that wherein the insulating substrate comprises: an effective area of the insulating substrate, a dummy area of the insulating substrate disposed outside the effective area, and a second unique code marked on the dummy area of the insulating substrate.
Yoshida while disclosing semiconductor device teaches (See, for example, Fig. 8) the insulating substrate comprises: an effective area (60) of the insulating substrate, a dummy area (61) of the insulating substrate disposed outside the effective area, and a second unique code marked (“the dummy patterns 62 serve also as element patterns constituting the symbol patterns. …the identification signs can be formed without reserving a region …”, See Col. 9 lines 3-15) on the dummy area (61) of the insulating substrate.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to mark a unique code taught by Phan on the dummy area of the insulating substrate, outside of the effective area, as taught by Yoshida because this would help place the identification signs in the dummy region without reserving a region intended for the exclusive use within the product area, preserving the full effective area for the final product.
In regards to claim 7, Nagamoto as modified above discloses (See, for example, Fig. 11, Phan) that wherein the first unique code of the second metal plate comprises a second unique code information of the insulating substrate (“the first barcode encoding … storing the wafer
information and data sufficient to relate the wafer information to the first barcode …
marking an integrated circuit being fabricated on the wafer with one or more
second barcodes….
marking a packaged integrated circuit fabricated from the wafer with one or more
third barcodes…” See claims 26 and 30). In the combination, the first unique code on the
second metal plate comprises information of the second unique code of the insulating substrate,
enabling the final substrate level code to be related back to the individual insulating substrate’s
identity and history for the traceability purposes taught by Phan.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Nagatomo in view of
Phan and Yoshida as applied to claim 6 above, and further in view of Lo et al. (US
2007/0220742 A1, hereinafter “Lo”).
In regards to claim 8, Nagamoto as modified above discloses that the heat dissipation substrate including the second unique code marked on the dummy area of the insulating substrate.
However, Nagamoto as modified above further fails to explicitly teach that wherein the second
unique code comprises a rectangular or square shape, and wherein a vertex of the second unique
code and a vertex of the effective area are arranged to face each other.
Lo while disclosing a method for fabricating identification code teaches (See, for example, Figs. 2, 3A-3C) the second unique code comprises a rectangular or square shape (See, 128a, 128b, 1128c) , and wherein a vertex of the second unique code and a vertex of the effective area are arranged to face each other (unpatterned non-circuit area A2 of a metallic film 120 distinct from the circuit area A1 comprising the circuits 122, bond pad 124, and conductive through hole 125, See Par [0019] and [0020]; As to the a vertex of the second unique code and a vertex of the effective area are being arranged to face each other, a vertex is a dimensionless point with no extend, surface, or inherent orientation; a point cannot “face” in a direction the way a surface or edges does, and as between any two points each lies opposite the other along the connecting line, any point in space is facing any other point.).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to further modify Nagamoto by Lo because this would improve the effectiveness of production management and quality control, and further enables to track the source, and accordingly to find out the possible root cause for the failure with the identification code.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Nagamoto in view of Terasaki et al. (USPN 9786577 B2, hereinafter “Terasaki”) and Phan.
In regards to claim 10, Nagamoto discloses all limitations of claim 9 above except that wherein
the third metal plate comprises a circuit pattern electrically connected to a power semiconductor
device, and the second metal plate comprises a unique code.
Terasaki while disclosing a power module substrate teaches (See, for example, Fig. 1)
wherein the third metal plate (12B) comprises a circuit pattern electrically connected to a power
semiconductor device (30).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Nagamoto by Terasaki because this would help prevent the deterioration o the bonding quality, the rise of the thermal resistance, and the breakage of the ceramic substrate.
However, Nagamoto modified by Terasaki is silent about that the second metal plate comprises a unique code.
Phan teaches (see, for example, Figs. 3, 6 and 11) the second metal plate comprises a marked first unique code (“The barcode data store 610 can store information including, but not limited to, data for interpreting barcodes, data for mapping barcode codes to wafer information, rules for interpreting barcodes and processing status of one or more wafers. The barcode data store 610 thus facilitates improving integrated circuit manufacturing by providing data concerning wafers in one or more phases of integrated circuit manufacture.”, See Col. 10 lines 20-31; “The barcode reader 330 can pass a wafer, and/or information concerning a wafer… distinguishing between wafers based on supplier, distinguishing between wafers based on materials in the wafer and distinguishing between wafers based on stages of processing through which a wafer has passed. By way of illustration, wafers of a first thickness can be routed to a first destination by the sorter 340 while wafers of a second thickness can be routed to a second destination.”, See Col. 7 lines10-26).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to incorporate the mark of Phan on the second metal layer of the Nagamoto substrate because this would help identify and history for the traceability purposes; and ensures efficient integrated circuit manufacturing.
Claims 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Nagamoto in view of Lowry et al. (USPN 7759778 B2, hereinafter “Lowry”).
In regards to claim 13, Nagamoto discloses (See, for example, Fig. 1) a power semiconductor module (1), comprising a first heat dissipation substrate (10); a power semiconductor device (3) disposed on the first heat dissipation substrate (10); wherein the first heat dissipation substrate (10) or the second heat dissipation substrate comprises the heat dissipation substrate according to claim 1.
Nagamoto fails to explicitly teach that a second heat dissipation substrate disposed on the power semiconductor device,
Lowry while disclosing semiconductor power module with direct bonding and double-sided cooling teaches (See, for example, Fig. 2E) a second heat dissipation substrate (22) disposed on
the power semiconductor device (“the power modules 10, 10’ are overmolded with an encapsulant 20, 20’ …”, See, for example, Col. 2 lines 28-44).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Nagamoto by Lowry because this would help optimize reliability and heat rejection.
In regards to claim 15, Nagatomo discloses (See, for example, Fig. 1) that wherein the first thickness (t1 ) of the first metal plate (12) is thinner than the second thickness (t2 ) of the second metal plate (13).
Claims 16, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Nagamoto in view of Lowry as applied to claim 13 above, and further in view of Phan.
In regards to claims 16, Nagatomo discloses (See, for example, Fig. 1) wherein the first metal plate (12) comprises a circuit pattern electrically connected to a power semiconductor device (See, for example, “circuit layer”, Abstract).
However, Nagatomo is silent about the second metal plate comprises a marked first unique code.
Phan while disclosing a semiconductor wafer marking teaches (see, for example, Figs. 3, 6 and 11) the second metal plate comprises a marked first unique code (“The barcode data store 610 can store information including, but not limited to, data for interpreting
barcodes, data for mapping barcode codes to wafer information, rules for interpreting barcodes and processing status of one or more wafers. The barcode data store 610 thus
facilitates improving integrated circuit manufacturing by providing data concerning wafers in one or more phases of integrated circuit manufacture.”, See Col. 10 lines 20-31;
“The barcode reader 330 can pass a wafer, and/or information concerning a wafer… distinguishing between wafers based on supplier, distinguishing between wafers based on
materials in the wafer and distinguishing between wafers based on stages of processing through which a wafer has passed. By way of illustration, wafers of a first thickness can be
routed to a first destination by the sorter 340 while wafers of a second thickness can be routed to a second destination.”, See Col. 7 lines10-26).
Therefore, it would have been obvious to one having ordinary skill in the art before the
effective filing date of the invention to incorporate the mark of Phan on the second metal layer of
the Nagamoto substrate because this would help identify and history for the traceability
purposes; and ensures efficient integrated circuit manufacturing.
In regards to claim 17, Nagamoto as modified above discloses (See, for example, Figs. 3, 6 and
11, Phan) that wherein the first unique code comprises thickness information of the insulating
substrate (See, for example, Col. 7 lines 10-26).
In regards to claim 18, Nagamoto as modified above discloses (See, for example, Figs. 3, 6 and 11, Phan) that wherein the first unique code comprises thickness information of at least one of the first metal plate and the second metal plate (“…The wafer 100 is marked with a barcode
110…The bar code 110 can encode information include, but not limited to, …conditions under which the wafer 100 was produced and properties of the manufactured wafer. The
properties of the manufactured wafer 100 can include … thickness…”, See Col. 5 lines 21-39; See also Col. 7 lines 10-26).
Claims 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nagamoto in view of Lowry as applied to claim 13 above, and further in view of Liang (USPN 9941234 B2, hereinafter “Liang”).
In regards to claim 14, Nagamoto as modified above discloses except that wherein the first heat dissipation substrate or the second heat dissipation substrate further comprises a power
semiconductor device bonded to a circuit pattern of the first metal plate, and further comprising a
bonding layer bonded between the circuit pattern of the first metal plate and the power semiconductor device by any one of sintering bonding, soldering bonding, or ultrasonic
bonding (claim 14); and a power converter comprising the power semiconductor module of claim 13 (claim 20).
Liang while disclosing packaging of power modules teaches (See, for example, Figs. 2 and 7)
wherein the first heat dissipation substrate (48)or the second heat dissipation substrate (46)
further comprises a power semiconductor device (22, 24) bonded to a circuit pattern (“Electrical
interconnection among the switch dies may be achieved by bonding the switch dies to two
(top and bottom) copper (Cu) substrates 46 an d48, which may be patterned to match with
pad layout on the semiconductor dies.”, See Col. 3 lines 55-67) of the first metal plate (46/48),
and further comprising a bonding layer bonded between the circuit pattern of the first metal plate
and the power semiconductor device by any one of sintering bonding, soldering bonding, or
ultrasonic bonding (“Die attach bonds between the semiconductor dies 22, 24 and the substrates 46 and 48 … Exemplary bonding methods may include solders and soldering,
…sintering…”, See, for example, Col. 5 lines 27-41); and a power converter (“…basic circuit for various automotive power converters…”, See Col. 3 lines 20-21) comprising the power semiconductor module of claim 13.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Nagamoto by Liang because this would help
reduces electrically parasitic inductance by reducing enclosed area of main power loop, reduce thermal resistance in each thermal path to provide superior cooling of power stage for reduced temperature and increased power density.
Claims 19 are rejected under 35 U.S.C. 103 as being unpatentable over Nagamoto in view of Lowry and Liang (USPN 9941234 B2, hereinafter “Liang”).
In regards to claim 19, Nagamoto discloses (See, for example, Fig. 1) a power semiconductor module (1), comprising:
a first heat dissipation substrate (10);
a power semiconductor device (3) disposed on the first heat dissipation substrate (10);
and wherein the first heat dissipation substrate (10) or the second heat dissipation substrate comprises the heat dissipation substrate according to claim 9.
Nagamoto fails to explicitly teach that a second heat dissipation substrate disposed on the power semiconductor device,
Lowry while disclosing semiconductor power module with direct bonding and double sided cooling teaches (See, for example, Fig. 2E) a second heat dissipation substrate (22) disposed on the power semiconductor device (“the power modules 10, 10’ are overmolded with an
encapsulant 20, 20’ …”, See, for example, Col. 2 lines 28-44).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Nagamoto by Lowry because this would help optimize reliability and heat rejection.
Nagamoto as modified by Lowry further fails to explicitly teach that further comprises a power semiconductor device bonded to a circuit pattern of the third metal plate, and a bonding layer bonded between the circuit pattern of the third metal plate and the power semiconductor
device using a phase change bonding method.
Liang discloses (See, for example, Figs. 2 and 7) that further comprises a power
semiconductor device (22, 24) bonded to a circuit pattern of the third metal plate, and a bonding
layer bonded between the circuit pattern (“Electrical interconnection among the switch dies
may be achieved by bonding the switch dies to two (top and bottom) copper (Cu) substrates
46 an d48, which may be patterned to match with pad layout on the semiconductor dies.”, See Col. 3 lines 55-67) of the third metal plate and the power semiconductor device (22, 24)
using a phase change bonding method (“Die attach bonds between the semiconductor dies 22,
24 and the substrates 46 and 48 … Exemplary bonding methods may include solders and
soldering, …and solid and/or liquid diffusion bonding”, See, for example, Col. 5 lines 27-
41).
Therefore, it would have been obvious to one having ordinary skill in the art before the
effective filing date of the invention to modify Nagamoto by Liang because this would help
reduces electrically parasitic inductance by reducing enclosed area of main power loop, reduce
thermal resistance in each thermal path to provide superior cooling of power stage for reduced
temperature and increased power density.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
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