DETAILED ACTION
Claims 1-20 remain pending in the present application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/13/26 has been entered.
Response to Arguments
Applicant’s arguments, filed 4/13/26, with respect to 35 U.S.C. §112 have been fully considered and are persuasive. The rejection of claim 15 has been withdrawn.
Applicant’s arguments, filed 4/13/26, with respect to 35 U.S.C. §102 and §103 have been fully considered and are persuasive. The rejection of claims 1-20 has been withdrawn.
The Double Patenting rejection from the first office action of 6/12/25 is maintained. This rejection WILL NOT be held in abeyance. A proper response to this Double Patenting rejection is to amend the claims to overcome the rejection or to file a terminal disclaimer. In the office actions mailed on 1/13/26 and 3/19/26, applicant was reminded that the request to hold in abeyance is NOT a proper response. This the third time applicant is being reminded.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-21 of U.S. Patent No. 10,956,262 . Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the pending claims are fully contained within the patented claims. Therefore given the patented claims, the pending claims would have been obvious to a person having ordinary skill in the art at the time of filing of the present application.
18/679341
US 10956262
1. A method comprising:
starting a deferred operation period of a memory system in response to a predefined condition in the memory system;
issuing a command to a memory bank of the memory system in response to an operation received from a processor;
generating ECC data prior to receiving a response to the command from the memory bank;
caching the ECC data in a local cache; and returning a result of the command to the processor while the ECC data is present in the local cache.
1. A method comprising: starting a deferred period of operation of a memory system in response to detecting the satisfaction of a condition;
receiving an operation from a processor during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; executing the operation and
issuing a command to a memory bank of the memory system, wherein the command does not include error code correction (ECC) data;
generating ECC data prior to receiving a response to the command from the memory bank;
caching the ECC data in a local cache; returning a result of the command to the processor while the ECC data is present in the local cache;
detecting an end of the deferred period of operation; and executing the ECC operations after the end of the deferred period.
2. The method of claim 1, wherein the condition is based on: a receipt of a second command to start the deferred operation period from the processor; or a data bus utilization above a predetermined threshold.
2. The method of claim 1, the detecting the satisfaction of the condition comprising detecting one of: a receipt of a second command to start the deferred period from the processor; or a data bus utilization above a predetermined threshold.
1. A method comprising:
starting a deferred operation period of a memory system in response to a predefined condition in the memory system;
issuing a command to a memory bank of the memory system in response to an operation received from a processor;
generating ECC data prior to receiving a response to the command from the memory bank;
caching the ECC data in a local cache; and
returning a result of the command to the processor while the ECC data is present in the local cache.
8. A non-transitory computer-readable storage medium for tangibly storing computer program instructions capable of being executed by a computer processor, the computer program instructions defining the steps of: starting a deferred period of operation of a memory system in response to detecting the satisfaction of a condition;
receiving an operation from a host processor during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; executing the operation and
issuing a command to a memory bank of the memory system, wherein the command does not include error code correction (ECC) data;
generating ECC data prior to receiving a response to the command from the memory bank;
caching the ECC data in a local cache;
returning a result of the command to the host processor while the ECC data is present in the local cache;
detecting an end of the deferred period of operation; and executing the ECC operations after the end of the deferred period.
3. The method of claim 1, further comprising:
receiving the operation during the deferred operation period,
the operation comprising a read or write operation access one or more memory banks of the memory system; and
executing the operation prior to issuing the command to the memory bank of the memory system.
Claim 1…
receiving an operation from a processor during the deferred period,
the operation comprising a read or write operation access one or more memory banks of the memory system;
executing the operation and …
in claim 1 this operation occurs ‘prior to’
4. The method of claim 3, the operation comprising a write operation and the generating of the ECC data comprising:
generating ECC parity bits based on data in the write operation; and
storing the ECC parity bits and an address associated with the data in the local cache.
4. The method of claim 1, the operation comprising a write operation and the generating ECC data
comprising:
generating ECC parity bits based on data in the write operation; and
storing the ECC parity bits and an address associated with the data in the local cache.
5. The method of claim 4, further comprising
writing the ECC parity bits to the memory bank using the address.
5. The method of claim 4, the executing the ECC operations comprising
writing the ECC parity bits to the memory bank using the address.
6. The method of claim 3, the operation comprising a read operation and the generating of the ECC data comprising generating an ECC syndrome based on data in the read operation; and storing the ECC syndrome and an address associated with the data in the local cache.
6. The method of claim 1, the operation comprising a read operation and the generating ECC data comprising: generating an ECC syndrome based on data in the read operation; and storing the ECC syndrome and an address associated with the data in the local cache.
7. The method of claim 6, further comprising: detecting a mismatch using the ECC syndrome; and in response to detecting the mismatch, alerting the processor that an error executing the read operation occurred.
7. The method of claim 5, the executing the ECC operations comprising: detecting a mismatch using the ECC syndrome; and in response to detecting the mismatch, alerting the processor that an error executing the read operation occurred
8. The method of claim 1, further comprising:
detecting an end of the deferred operation period; and executing ECC operations after the end of the deferred operation period.
Claim 8…
detecting an end of the deferred period of operation; and executing the ECC operations after the end of the deferred period.
9. The method of claim 8,
the detecting of the end of the deferred operation period comprising detecting one of:
a receipt of a third command to stop the deferred operation period from the processor; a data bus utilization below a predetermined threshold; or the local cache is full.
9. The non-transitory computer-readable storage medium of claim 8,
the detecting the satisfaction of the condition comprising detecting one of;
a receipt of a second command to start the deferred period from the host processor; or a data bus utilization above a predetermined threshold.
10. A non-transitory computer-readable storage medium for tangibly storing computer program instructions which, when executed by a computer processor, cause the computer processor to perform a method, comprising:
starting a deferred operation period of a memory system in response to detecting a satisfaction of a
condition;
issuing a command to a memory bank of the memory system in response to an operation received from a processor;
generating ECC data prior to receiving a response to the command from the memory bank;
caching the ECC data in a local cache; and
returning a result of the command to the processor while the ECC data is present in the local cache.
8. A non-transitory computer-readable storage medium for tangibly storing computer program instructions capable of being executed by a computer processor, the computer program instructions defining the steps of:
starting a deferred period of operation of a memory system in response to detecting the satisfaction of a condition;
receiving an operation from a host processor during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; executing the operation and
issuing a command to a memory bank of the memory system, wherein the command does not include error code correction (ECC) data;
generating ECC data prior to receiving a response to the command from the memory bank;
caching the ECC data in a local cache;
returning a result of the command to the host processor while the ECC data is present in the local cache; detecting an end of the deferred period of operation; and executing the ECC operations after the end of the deferred period.
11. The non-transitory computer-readable storage medium of claim 10, wherein the method further comprises: receiving the operation during the deferred operation period, the operation comprising a read or write operation access one or more memory banks of the memory system; and
executing the operation prior to issuing the command to the memory bank of the memory system.
Claim 8…
receiving an operation from a host processor during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; executing the operation and…
See claim 8- this operation occurs prior to…
12. The non-transitory computer-readable storage medium of claim 10, the detecting the satisfaction of the condition comprising detecting one of: a receipt of a second command to start the deferred operation period from the processor; or
a data bus utilization above a predetermined threshold.
10. The non-transitory computer-readable storage medium of claim 8, the detecting the end of the deferred period comprising detecting one of:
a receipt of a third command to stop the deferred period from the host processor;
a data bus utilization below a predetermined threshold; or the local cache is full.
13. The non-transitory computer-readable storage medium of claim 10, the operation comprising
a write operation and the generating of the ECC data comprising:
generating ECC parity bits based on data in the write operation; and
storing the ECC parity bits and an address associated with the data in the local cache.
11. The non-transitory computer-readable storage medium of claim 8, the operation comprising
a write operation and the generating ECC comprising:
generating ECC parity bits based on the data in the write operation; and storing the ECC parity bits and an address associated with the data in the local cache.
14. The non-transitory computer-readable storage medium of claim 10, the operation comprising a read operation and the generating of the ECC data comprising
generating an ECC syndrome based on data in the read operation; and
storing the ECC syndrome and an address associated with the data in the local cache.
13. The non-transitory computer-readable storage medium of claim 8,
the operation comprising a read operation and the generating
ECC data comprising:
generating an ECC syndrome based on data in the read operation; and
storing the ECC syndrome and an address associated with the data in the local cache.
15. A memory system comprising:
a plurality of memory banks;
a bus connected to the memory banks; and a controller connected to the bus, the controller configured to perform operations of:
starting a deferred operation period of the memory system
in response to detecting a satisfaction of a condition;
issuing a command to a memory bank of the memory system in response to an operation received from a processor;
generating ECC data prior to receiving a response to the command from the memory bank;
caching the ECC data in a local cache; and returning a result of the command to the processor while the ECC data is present in the local cache.
15. A memory system comprising:
a plurality of memory banks;
a bus connected to the memory banks; and a controller connected to the bus, the controller configured to perform the operations of:
starting a deferred period of operation from a processor of the memory system in response to detecting the satisfaction of a condition;
receiving an operation during the deferred period, the operation comprising a read or write operation access the memory banks; executing the operation and issuing a command to the memory banks of the memory system, wherein the command does not include error code correction (ECC) data;
generating ECC data prior to receiving a response to the command from the memory bank;
caching the ECC data in a local cache; returning a result of the command to the processor while the ECC data is present in the local cache;
detecting an end of the deferred period of operation; and executing the ECC operations after the end of the deferred period.
16. The memory system of claim 15, the operations further comprising: receiving the operation during the deferred operation period, the operation comprising a read or write operation access one or more memory banks of the memory system; and executing the operation
prior to issuing the command to the memory bank of the memory system.
Claim 15. …
receiving an operation during the deferred period, the operation comprising a read or write operation access the memory banks; executing the operation and issuing a command to the memory banks of the memory system…
See claim 15- this operation occurs prior to…
17. The memory system of claim 15, the detecting the satisfaction of the condition comprising detecting one of: a receipt of a second command to start the deferred operation period from the processor; or a data bus utilization above a predetermined threshold.
16. The memory system of claim 15, the detecting the satisfaction of the condition comprising detecting one of: a receipt of a second command to start the deferred period from the processor; or a data utilization of the bus above a predetermined threshold.
18. The memory system of claim 15, the operation comprising a write operation and the generating of the ECC data comprising: generating ECC parity bits based on data in the write operation; and storing the ECC parity bits and an address associated with the data in the local cache.
18. The memory system of claim 15, the operation comprising a write operation and the generating ECC data comprising: generating ECC parity bits based on data in the write operation; and storing the ECC parity bits and an address associated with the data in the local cache.
19. The memory system of claim 18, further comprising writing the ECC parity bits to the memory bank using the address.
19. The memory system of claim 18, the executing the ECC operations comprising writing the ECC parity bits to the memory bank using the address.
20. The memory system of claim 15, the operation comprising a read operation and the generating of the ECC data comprising generating an ECC syndrome based on data in the read operation; and storing the ECC syndrome and an address associated with the data in the local cache.
20. The memory system of claim 15, the operation comprising a read operation and the generating ECC data comprising: generating an ECC syndrome based on data in the read operation; and storing the ECC syndrome and an address associated with the data in the local cache.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,001,281. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the pending claims are fully contained within the patented claims. Therefore given the patented claims, the pending claims would have been obvious to a person having ordinary skill in the art at the time of filing of the present application.
18/679341
US 12001281
1. A method comprising:
starting a deferred operation period of a memory system in response to a predefined condition in the memory system;
issuing a command to a memory bank of the memory system
in response to an operation received from a processor;
generating ECC data prior to receiving a response to the command from the memory bank;
caching the ECC data in a local cache; and returning a result of the command to the processor while the ECC data is present in the local cache.
1. A method comprising:
starting a deferred period of operation of a memory system in response to detecting a satisfaction of a condition, wherein, during the deferred period of operation, an error code correction (ECC) portion of a memory bank is not accessed during operations;
issuing a command to read data from or write data to the memory bank of the memory system
in response to an operation received from a processor during the deferred period of operation;
generating ECC data prior to receiving a response to the command from the memory bank during the deferred period of operation;
caching the ECC data in a local cache; and returning a result of the command to the processor while the ECC data is present in the local cache.
2. The method of claim 1, wherein the condition is based on:
a receipt of a second command to start the deferred operation period from the processor; or a data bus utilization above a predetermined threshold.
3. The method of claim 1, the detecting the satisfaction of the condition comprising detecting one of:
a receipt of a second command to start the deferred period from the processor; or a data bus utilization above a predetermined threshold.
3. The method of claim 1, further comprising: receiving the operation during the deferred operation period, the operation comprising a read or write operation access one or more memory banks of the memory system; and executing the operation prior to issuing the command to the memory bank of the memory system.
Claim 1. …
read data from or write data to the memory bank of the memory system in response to an operation received from a processor during the deferred period of operation;
4. The method of claim 3, the operation comprising a write operation and the generating of the ECC data comprising:
generating ECC parity bits based on data in the write operation; and
storing the ECC parity bits and an address associated with the data in the local cache.
4. The method of claim 2, the operation comprising a write operation and the generating ECC data comprising:
generating ECC parity bits based on data in the write operation; and
storing the ECC parity bits and an address associated with the data in the local cache.
5. The method of claim 4, further comprising writing the ECC parity bits to the memory bank using the address.
5. The method of claim 4, further comprising writing the ECC parity bits to the memory bank using the address.
6. The method of claim 3, the operation comprising a read operation and the generating of the ECC data comprising generating an ECC syndrome based on data in the read operation; and storing the ECC syndrome and an address associated with the data in the local cache.
6. The method of claim 2, the operation comprising a read operation and the generating ECC data comprising generating an ECC syndrome based on data in the read operation; and storing the ECC syndrome and an address associated with the data in the local cache.
7. The method of claim 6, further comprising:
detecting a mismatch using the ECC syndrome; and in response to detecting the mismatch, alerting the processor that an error executing the read operation occurred.
7. The method of claim 6, further comprising:
detecting a mismatch using the ECC syndrome; and in response to detecting the mismatch, alerting the processor that an error executing the read operation occurred.
8. The method of claim 1, further comprising:
detecting an end of the deferred operation period; and executing ECC operations after the end of the deferred operation period.
8. The method of claim 1, further comprising:
detecting an end of the deferred period of operation; and executing ECC operations after the end of the deferred period.
9. The method of claim 8, the detecting of the end of the deferred operation period comprising detecting one of:
a receipt of a third command to stop the deferred operation period from the processor;
a data bus utilization below a predetermined threshold; or
the local cache is full.
9. The method of claim 8, the detecting the end of the deferred period comprising detecting one of:
a receipt of a third command to stop the deferred period from the processor;
a data bus utilization below a predetermined threshold; or
the local cache is full.
10. A non-transitory computer-readable storage medium for tangibly storing computer program instructions which, when executed by a computer processor, cause the computer processor to perform a method, comprising:
starting a deferred operation period of a memory system in response to detecting a satisfaction of a condition;
issuing a command to a memory bank of the memory system in response to an operation received from a processor;
generating ECC data prior to receiving a response to the command from the memory bank;
caching the ECC data in a local cache; and returning a result of the command to the processor while the ECC data is present in the local cache.
10. A non-transitory computer-readable storage medium for tangibly storing computer program instructions capable of being executed by a computer processor, the computer program instructions defining steps of:
starting a deferred period of operation of a memory system in response to detecting a satisfaction of a condition, wherein, during the deferred period of operation, an error code correction (ECC) portion of a memory bank is not accessed during operations;
issuing a command to read data from or write data to the memory bank of the memory system in response to an operation received from a processor during the deferred period of operation; generating ECC data prior to receiving a response to the command from the memory bank during the deferred period of operation;
caching the ECC data in a local cache; and returning a result of the command to the processor while the ECC data is present in the local cache.
11. The non-transitory computer-readable storage medium of claim 10, wherein the method further comprises:
receiving the operation during the deferred operation period, the operation comprising a read or write operation access one or more memory banks of the memory system; and
executing the operation prior to issuing the command to the memory bank of the memory system.
11. The non-transitory computer-readable storage medium of claim 10, the computer program instructions further defining steps of:
receiving the operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; and
executing the operation prior to issuing the command to the memory bank of the memory system.
12. The non-transitory computer-readable storage medium of claim 10, the detecting the satisfaction of the condition comprising detecting one of: a receipt of a second command to start the deferred operation period from the processor;
or a data bus utilization above a predetermined threshold.
12. The non-transitory computer-readable storage medium of claim 10, the detecting the satisfaction of the condition comprising detecting one of: a receipt of a second command to start the deferred period from the processor;
or a data bus utilization above a predetermined threshold.
13. The non-transitory computer-readable storage medium of claim 10, the operation comprising a write operation and the generating of the ECC data comprising: generating ECC parity bits based on data in the write operation; and storing the ECC parity bits and an address associated with the data in the local cache.
13. The non-transitory computer-readable storage medium of claim 10, the operation comprising a write operation and the generating ECC data comprising: generating ECC parity bits based on data in the write operation; and storing the ECC parity bits and an address associated with the data in the local cache.
14. The non-transitory computer-readable storage medium of claim 10, the operation comprising a read operation and the generating of the ECC data comprising generating an ECC syndrome based on data in the read operation; and
storing the ECC syndrome and an address associated with the data in the local cache.
14. The non-transitory computer-readable storage medium of claim 10, the operation comprising a read operation and the generating ECC data comprising generating an ECC syndrome based on data in the read operation; and
storing the ECC syndrome and an address associated with the data in the local cache.
15. A memory system comprising:
a plurality of memory banks;
a bus connected to the memory banks; and
a controller connected to the bus, the controller configured to perform operations of:
starting a deferred operation period of the memory system in response to detecting a satisfaction of a condition;
issuing a command to a memory bank of the memory system in response to an operation received from a processor;
generating ECC data prior to receiving a response to the command from the memory bank;
caching the ECC data in a local cache; and returning a result of the command to the processor while the ECC data is present in the local cache.
15. A memory system comprising:
a plurality of memory banks;
a bus connected to the memory banks; and
a controller connected to the bus, the controller configured to perform operations of:
starting a deferred period of operation of a memory system in response to detecting a satisfaction of a condition, wherein, during the deferred period of operation, an error code correction (ECC) portion of a memory bank is not accessed during operations; issuing a command to read data from or write data to the memory bank of the memory system in response to an operation received from a processor during the deferred period of operation;
generating ECC data prior to receiving a response to the command from the memory bank during the deferred period of operation;
caching the ECC data in a local cache; and returning a result of the command to the processor while the ECC data is present in the local cache.
16. The memory system of claim 15, the operations further comprising: receiving the operation during the deferred operation period, the operation comprising a read or write operation access one or more memory banks of the memory system; and
executing the operation prior to issuing the command to the memory bank of the memory system.
16. The memory system of claim 15, the operations further comprising: receiving the operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; and
executing the operation prior to issuing the command to the memory bank of the memory system.
17. The memory system of claim 15, the detecting the satisfaction of the condition comprising detecting one of: a receipt of a second command to start the deferred operation period from the processor; or a data bus utilization above a predetermined threshold.
17. The memory system of claim 15, the detecting the satisfaction of the condition comprising detecting one of: a receipt of a second command to start the deferred period from the processor; or a data bus utilization above a predetermined threshold.
18. The memory system of claim 15, the operation comprising a write operation and the generating of the ECC data comprising:
generating ECC parity bits based on data in the write operation; and storing the ECC parity bits and an address associated with the data in the local cache.
18. The memory system of claim 15, the operation comprising a write operation and the generating ECC data comprising:
generating ECC parity bits based on data in the write operation; and storing the ECC parity bits and an address associated with the data in the local cache.
19. The memory system of claim 18, further comprising writing the ECC parity bits to the memory bank using the address.
19. The memory system of claim 18, further comprising writing the ECC parity bits to the memory bank using the address.
20. The memory system of claim 15, the operation comprising a read operation and the generating of the ECC data comprising generating an ECC syndrome based on data in the read operation; and storing the ECC syndrome and an address associated with the data in the local cache.
20. The memory system of claim 15, the operation comprising a read operation and the generating ECC data comprising generating an ECC syndrome based on data in the read operation; and storing the ECC syndrome and an address associated with the data in the local cache.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Syzdek et al. US Pub 2008/0072117 teaches an NVM device switches from the ECC enabled mode to an ECC disabled mode (error correction disabled mode) in response to a first condition. After the NVM device 16 is in the ECC disabled mode, at least a portion of an address unit 23 (or at least a portion of the addressable unit (e.g., the entire or a portion of the address unit 23) is programmed in the ECC disabled mode as illustrated in process 54. In one embodiment, the at least a portion of the address unit 23 that is programmed is only a few bits of a full address. For example, only 6 bits of a 64 bit address may be written. After a second condition, such as the desired amount of data is programmed into the memory array 24, the NVM device 16 switches from the ECC disabled mode to the ECC fill mode.
Huang US Patent 7644341, teaches correcting a soft error in a memory circuit during a stand-by mode which comprises deactivating or suspending an ECC logic circuit for scanning and correcting errors until a normal read or write operation is over.
This is a RCE of applicant's earlier Application No. 18/679341. All claims are identical to, patentably indistinct from, or have unity of invention with the invention claimed in the earlier application (that is, restriction (including lack of unity) would not be proper) and could have been finally rejected on the grounds and art of record in the next Office action if they had been entered in the earlier application. Accordingly, THIS ACTION IS MADE FINAL even though it is a first action in this case. See MPEP § 706.07(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CYNTHIA H BRITT whose telephone number is (571)272-3815. The examiner can normally be reached Monday - Thursday 8-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571)270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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CYNTHIA H. BRITT
Primary Examiner
Art Unit 2111
/CYNTHIA BRITT/Primary Examiner, Art Unit 2111
Prosecution Insights