DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/30/2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 1, 9, 11, and 17 have been amended. Claims 1-7 and 9-20 are currently pending.
Response to Arguments
Applicant's arguments filed have been fully considered but they are not persuasive.
Regarding Applicant’s arguments that Ahmad does not teach the interface coupled between the DPE array and a memory controller of claim 1, the Examiner respectfully disagrees.
Ahmad discloses a system on a chip (SoC) (See Ahmad: Fig. 1, SoC 100; Col. 4, Lines 49-50, System-on-Chip (SoC) 100; i.e. SoC of claim 1) with a hardware accelerator including data processing engines (DPEs) (Figs. 1 and 2, DPE array 102; Col. 28, Lines 22-23, hardware acceleration engines include, but are not limited to, DPEs; i.e. DPEs of claim 1) and an interface circuitry (Fig. 2, SoC interface block 206; i.e. interface circuitry of claim 1), wherein the DPEs are in a first clock domain that uses a first clock (Fig. 2, DPE array 102 with DPEs is in a first clock domain; Col. 8, Lines 5-6, DPE array 102 includes a single clock domain) and wherein there is a second clock domain (Fig. 1, Portions of the SoC are in a second clock domain; Col. 8, Lines 6-8, Other subsystems such as NoC 108, PL 104, PS 106, and the various hardwired circuit blocks 110 may be in one or more separate or different clock domain(s)), wherein an interface further couples the hardware accelerator to other SoC components (Fig. 1, NoC 108 couples SoC 100 components together). While Applicant argues that the interface is not coupled to a memory controller, Figure 6 of Ahmad shows where the Noc 108 (Figs. 1 and 6 are the same embodiment showing the NoC 108; i.e. the interface) is coupled to programmable logic (PL) 104, wherein the programmable logic 104 includes a memory controller (Col. 28, Lines 35-37, memory that may be accessible using hardwired memory controllers and/or custom memory controllers implemented in the PL regions 104). Thus, the interface 108 of Figures 1, 2, and 6 are coupled directly a memory controllers implemented on programmable logic 104 (Col. 24, Lines 9-11, DPE array 102 can communicate with each other or other subsystems (e.g., the PS 106 and/or a memory controller) via the NoC 108).
Applicant’s arguments with respect to claims 1, 11, and 17 limitations of wherein the DPEs are in a first clock domain and the interface circuitry is in a second clock domain that is separate from the first clock domain have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
See Detailed Rejection Below.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-7 and 10-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 and 9-20 of copending Application No. 18/394,675 in view of Noguera Serra (US 2022/0100691).
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
As per claims 1-7 and 10-20,
Instant Application
US Application 18/394,675
Claim 1: A system on a chip (SoC), comprising: a hardware accelerator comprising data processing engines (DPEs) and interface circuitry, wherein the DPEs are in a first clock domain that uses a first clock and the interface circuitry is in a second clock domain that is separate from the first clock domain and that uses a second clock with a different frequency than the first clock; and an interface communicatively coupling the hardware accelerator to other circuitry in the SoC, wherein the interface circuitry is configured to move data into and out of the hardware accelerator via the interface, wherein the interface is communicatively coupled between the DPEs and a memory controller; and wherein the second clock has a higher frequency than the first clock.
Claim 1: A system on a chip (SoC), comprising: at least one central processing unit (CPU); at least one graphics processing unit (GPU); a hardware accelerator comprising data processing engines (DPEs) and other circuitry that excludes DPEs, wherein the DPEs are in a first power or clock domain and the other circuitry is in a second power or clock domain, wherein the SoC is configured to turn off the first power or clock domain to disable the DPEs while the second power or clock domain remains turned on, wherein the hardware accelerator excludes the at least one GPU; and an interface communicatively coupling the CPU to the hardware accelerator.
Claim 2: The SoC of claim 1, wherein the other circuitry in the second power or clock domain comprises: a controller; a network on chip (NoC); and an Input-Output Memory Management Unit (IOMMU) comprising circuitry configured to perform a physical to virtual address translation, wherein the IOMMU is coupled to the DPEs via the NoC.
Claim 3: The SoC of claim 2, wherein the IOMMU is configured to translate virtual addresses used by the hardware accelerator to physical addresses used by the CPU before transmitting data from the hardware accelerator to the interface.
Note:
Claim 1 of US Application 18/394,675 teaches the italicized and underlined limitations of instant claim 1.
Claim 2 of US Application 18/394,675 teaches the bolded limitations of instant claim 1.
Claim 3 of US Application 18/394,675 teaches the italicized, underlined, and bolded limitations of instant claim 1.
Claims 1-3 of US Application 18/394,675 do not teach the italicized limitations of instant claim 1, however Noguera Serra (US 2022/0100691) teaches these limitations. See Below.
Claim 2: The SoC of claim 1, wherein the interface circuitry in the second clock domain comprises: an Input-Output Memory Management Unit (IOMMU) comprising circuitry configured to perform a physical to virtual address translation.
Claim 2: The SoC of claim 1, wherein the other circuitry in the second power or clock domain comprises: a controller; a network on chip (NoC); and an Input-Output Memory Management Unit (IOMMU) comprising circuitry configured to perform a physical to virtual address translation, wherein the IOMMU is coupled to the DPEs via the NoC.
Claim 3: The SoC of claim 2, wherein the other circuitry comprises at least one central processing unit (CPU), wherein the IOMMU is configured to translate virtual addresses used by the hardware accelerator to physical addresses used by the at least one CPU before transmitting data from the hardware accelerator to the interface.
Claim 3: The SoC of claim 2, wherein the IOMMU is configured to translate virtual addresses used by the hardware accelerator to physical addresses used by the CPU before transmitting data from the hardware accelerator to the interface.
Claim 4: The SoC of claim 3, wherein the CPU is in a different clock domain than the first clock domain.
Claim 6: The SoC of claim 1, wherein the CPU is in a different power or clock domain than the first power or clock domain.
Claim 5: The SoC of claim 4, wherein the CPU is in a third clock domain that is separate from the first and second clock domains.
Claim 7: The SoC of claim 6, wherein the CPU is in a third power or clock domain that is separate from the first and second power or clock domains.
Claim 6: The SoC of claim 2, wherein the interface circuitry further comprises a controller and a network on chip (NoC), wherein the controller and the IOMMU communicate with the DPEs through the NoC.
Claim 2: The SoC of claim 1, wherein the other circuitry in the second power or clock domain comprises: a controller;a network on chip (NoC); and an Input-Output Memory Management Unit (IOMMU) comprising circuitry configured to perform a physical to virtual address translation, wherein the IOMMU is coupled to the DPEs via the NoC.
Claim 4: The SoC of claim 2, wherein the controller communicates with the DPEs through the NoC.
Claim 7: The SoC of claim 6, wherein the controller communicates with a CPU only through the interface, wherein the interface is a second NoC, wherein the second NoC is larger than the NoC in the hardware accelerator.
Claim 5: The SoC of claim 2, wherein the controller communicates with the CPU only through the interface, wherein the interface is a second NoC, wherein the second NoC is larger than the NoC in the hardware accelerator.
Claim 10: The SoC of claim 1, wherein the DPEs are arranged in an array, wherein each of the DPEs comprises a core, a memory module, and an interconnect, wherein the interconnects in the DPEs are interconnected so that the DPEs are able to transmit data between each other.
Claim 9: The SoC of claim 1, wherein the DPEs are arranged in an array, wherein each of the DPEs comprises a core, a memory module, and an interconnect, wherein the interconnects in the DPEs are interconnected so that the DPEs are able to transmit data between each other.
Claim 11: A method, comprising: providing a hardware accelerator comprising DPEs in a first clock domain and interface circuitry in a second clock domain that is separate from the first clock domain; operating a first clock in the first clock domain at a first frequency; and operating a second clock in the second clock domain at a second frequency, wherein the interface circuitry is configured to move data into and out of the hardware accelerator via an interface, wherein the interface circuitry is communicatively coupled between the DPEs and a memory controller in a same SoC, and wherein the second clock has a higher frequency than the first clock.
Claim 11: A method, comprising: determining that DPEs in a hardware accelerator are idle, wherein the DPEs are in a first power or clock domain and other circuitry, that excludes DPEs, in the hardware accelerator are in a second power or clock domain, wherein the hardware accelerator is located on a system on a chip (SoC) which further comprises: at least one central processing unit (CPU); and at least one graphics processing unit (GPU), wherein the hardware accelerator excludes the at least one GPU; turning off the first power or clock domain but not the second power or clock domain so that the DPEs are disabled but the other circuitry remains operational; determining, after turning off the first power or clock domain, that the DPEs have work; and turning on the first power or clock domain so the DPEs are operational to perform the work.
Claim 12: The method of claim 11, wherein the other circuitry in the second power or clock domain comprises: a controller; a network on chip (NoC); and an Input-Output Memory Management Unit (IOMMU) comprising circuitry configured to perform a physical to virtual address translation, wherein the IOMMU is coupled to the DPEs via the NoC.
Claim 13: The method of claim 12, further comprising: translating, using the IOMMU, virtual addresses used by the hardware accelerator to physical addresses used by a CPU before transmitting data from the hardware accelerator to the CPU, wherein the CPU is in a same SoC as the hardware accelerator.
Note: Claims 11-13 of US Application 18/394,675 in view of Noguera Serra (US 2022/0100691) teaches instant claim 11 under similar rationale for instant claim 1.
Claim 12: The method of claim 11, wherein the interface circuitry in the second clock domain comprises: an IOMMU comprising circuitry configured to perform a physical to virtual address translation.
Claim 12: The method of claim 11, wherein the other circuitry in the second power or clock domain comprises: a controller; a network on chip (NoC); and an Input-Output Memory Management Unit (IOMMU) comprising circuitry configured to perform a physical to virtual address translation, wherein the IOMMU is coupled to the DPEs via the NoC.
Claim 13: The method of claim 12, further comprising:
translating, using the IOMMU, virtual addresses used by the hardware accelerator to physical addresses used by a CPU before transmitting data from the hardware accelerator to the CPU, wherein the CPU is in a same SoC as the hardware accelerator.
Claim 13: The method of claim 12, further comprising: translating, using the IOMMU, virtual addresses used by the hardware accelerator to physical addresses used by a CPU before transmitting data from the hardware accelerator to the CPU, wherein the CPU is in a same SoC as the hardware accelerator.
Claim 14: The method of claim 13, wherein the CPU is in a different clock domain than the first clock domain.
Claim 14: The method of claim 13, wherein the CPU is in a different power or clock domain than the first power or clock domain.
Claim 15: The method of claim 14, wherein the CPU is in a third clock domain that is separate from the first and second clock domains.
Claim 15: The method of claim 14, wherein the CPU is in a third power or clock domain that is separate from the first and second power or clock domains.
Claim 16: The method of claim 11, wherein the hardware accelerator is at least one of an artificial intelligence (AI) accelerator, a cryptography accelerator, or a compression accelerator.
Claim 16: The method of claim 11, wherein the hardware accelerator is at least one of an artificial intelligence (AI) accelerator, a cryptography accelerator, or a compression accelerator.
Claim 17: A system, comprising: an IC, comprising: a hardware accelerator comprising DPEs in a first clock domain and interface circuitry in a second clock domain that is separate from the first clock domain and, wherein, during operation, a first clock in the first clock domain has lower frequency than a second clock in the second clock domain, wherein the interface circuitry is configured to move data into and out of the hardware accelerator via an interface, and a memory controller, wherein the interface circuitry is communicatively coupled between the DPEs and the memory controller; and at least one memory coupled to the memory controller in the IC.
Claim 17: A system, comprising: an IC, comprising: at least one graphics processing unit (GPU);a hardware accelerator comprising DPEs in a first power or clock domain and other circuitry, that excludes DPEs, in a second power or clock domain, wherein the IC is configured to turn off the first power or clock domain to disable the DPEs while the other circuitry in the second power or clock domain remains operational, wherein the hardware accelerator excludes the at least one GPU, and a memory controller; and at least one memory coupled to the memory controller in the IC.
Claim 18: The system of claim 17, wherein the other circuitry in the second power or clock domain comprises: a controller; a network on chip (NoC); and an Input-Output Memory Management Unit (IOMMU) comprising circuitry configured to perform a physical to virtual address translation, wherein the IOMMU is coupled to the DPEs via the NoC.
Claim 19: The system of claim 18, wherein the IC comprises a CPU and an interconnect, wherein the interconnect couples the CPU to the controller and the IOMMU in the hardware accelerator.
Note:
Note: Claims 17-19 of US Application 18/394,675 in view of Noguera Serra (US 2022/0100691) teaches instant claim 17 under similar rationale for instant claim 1.
Claim 18: The system of claim 17, wherein the interface circuitry in the second clock domain comprises: an IOMMU comprising circuitry configured to perform a physical to virtual address translation.
Claim 18: The system of claim 17, wherein the other circuitry in the second power or clock domain comprises: a controller; a network on chip (NoC); and an Input-Output Memory Management Unit (IOMMU) comprising circuitry configured to perform a physical to virtual address translation, wherein the IOMMU is coupled to the DPEs via the NoC.
Claim 19: The system of claim 18, wherein the IC comprises a CPU and an interconnect, wherein the interconnect couples the CPU to a controller in the hardware accelerator and the IOMMU in the hardware accelerator.
Claim 19: The system of claim 18, wherein the IC comprises a CPU and an interconnect, wherein the interconnect couples the CPU to the controller and the IOMMU in the hardware accelerator.
Claim 20: The system of claim 17, wherein the first circuitry comprises DPEs arranged in an array, wherein each of the DPEs comprises a core, a memory module, and an interconnect, wherein the interconnects in the DPEs are interconnected so that the DPEs are able to transmit data between each other.
Claim 20: The system of claim 17, wherein the DPEs are arranged in an array, wherein each of the DPEs comprises a core, a memory module, and an interconnect, wherein the interconnects in the DPEs are interconnected so that the DPEs are able to transmit data between each other.
Claim 1 of US Application 18/394,675 discloses an SoC comprising a hardware accelerator comprising a DPE array in a first clock domain and a circuitry in a second clock domain and an interface coupling the hardware accelerator to SoC circuitry. While claim 1 of US Application 18/394,675 does not explicitly teach wherein the circuitry in a second clock domain is an interface circuitry configured to move data between the interface and the hardware accelerator, dependent claims 2-3 of US Application 18/394,675 does disclose these limitations as shown in the table above, with claim 2 of US Application 18/394,675 disclosing that the circuitry of the second clock domain includes an IOMMU which is an interface circuitry, and claim 3 of US Application 18/394,675 disclosing that the IOMMU moves data in and out between the interface and the hardware accelerator. It would have been obvious to incorporate the teachings of claims 2-3 of US Application 18/394,675 into claim 1 of US Application 18/394,675 as they are in the same embodiment of the SoC.
Claims 1-3 of US Application 18/394,675 do not teach the SoC comprising the interface circuitry is in a second clock domain that uses that is separate from the first clock domain and that uses a second clock with a different frequency than the first clock; and wherein the second clock has a higher frequency than the first clock.
These limitations are however known in the art as shown in Noguera Serra (US 2022/0100691). Noguera Serra teaches the SoC (Fig. 3, SoC 100) comprising the interface circuitry is in a second clock domain that is separate from the first clock domain (Figs. 3 and 4, Physical interface 306 uses a second clock frequency domain separate from the clock frequency of DPEs 402 of DPE array 110; Paragraph 0131, provides an asynchronous clock-domain crossing between DPE array 110 and another clock domain… Paragraph 0164, physical interface 306 and/or other dies coupled thereto operate at a different reference voltage and a different clock speed than DPEs 402) and that uses a second clock with a different frequency than the first clock, and wherein the second clock has a higher frequency than the first clock (Figs. 3, 4, and 7, Physical interface 306 can have a higher clock frequency than the DPEs; Paragraph 0165, providing an interface that transitions between the clock rate of physical interface 306 or other circuitry and/or other circuitry coupled thereto and the clock rate of DPEs 402… Paragraph 0030, clock signals of different clock domains may have different clock frequencies and/or phases).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified US Application 18/394,675’s SoC of claims 1-3 to incorporate the teachings of Noguera Serra and include separate clock domains within the single SoC, wherein the interface circuitry can use a second clock frequency that is higher than the first clock frequency of the DPE array, in order to provide compatibility between circuitry of varying types, thus providing flexibility to IC designers to implement different generations of circuit technologies and architectures (See Noguera Serra: Paragraph 0028).
Instant claims 11 and 17 are similar to instant claim 1 and thus instant claim 11 is rejected by claims 11-13 of US Application 18/394,675 in view of Noguera Serra and instant claim 17 is rejected by claims 17-19 of US Application 18/394,675 in view of Noguera Serra under similar rationale, respectively.
Dependent claims 2-7, 10, 12-16, and 18-20 are rejected over claims 1-7 and 9-20 of US Application 18/394,675 in view of Noguera Serra. See Table Above.
Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 of copending Application No. 18/394,675 in view of Noguera Serra (US 2022/0100691) and further in view of Nampoothiri (US 2018/0267595).
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Regarding instant claim 9, claims 1-3 of US Application 18/394,675 in view of Noguera Serra teaches instant claim 1 which instant claim 9 is dependent on. However, claims 1-3 of US Application 18/394,675 in view of Noguera Serra do not teach wherein the SoC is configured to increase and decrease a frequency of the second clock in response to data movement demand thresholds corresponding to the interface circuitry of instant claim 9.
These limitations are however known in the art as shown in Nampoothiri (US 2018/026795). Nampoothiri teaches the SoC (Fig. 1, SoC 100; Paragraph 0028, FIG. 1 illustrates example components and interconnections in a system-on-chip (SoC) 100) comprising wherein the SoC is configured to increase and decrease a frequency of the second clock in response to data movement demand thresholds (Fig. 2, Calculate demand thresholds in step 204 and increase/decrease clock frequency in step 206; Paragraph 0039, At 204, the CRM calculates an adjusted bandwidth for operating the memory based on the determined efficiency. At 206, the CRM adjusts at least one of a voltage or a clock frequency of the memory interface/bus to the memory based on the determined adjusted bandwidth) corresponding to the interface circuitry (Fig. 1, Memory interface/bus 126 changes clock frequency; Paragraph 0035, SoC typically adds up the bandwidth votes from multiple IP cores and then computes a minimum frequency to operate the memory interface/bus 126 needed for the bandwidth votes (referred to herein as DDR_BW_freq)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified US Application 18/394,675’s SoC of claims 1-3 in view of Noguera Serra to incorporate the teachings of Nampoothiri and enable the frequency of the interface circuitry to be increased or decreased based on demand thresholds in order to reduce power consumption in SoC devices by dynamically accounting for memory efficiency and keeping bus clocks at optimum levels to meet a desired performance level (See Nampoothiri: Paragraph 0026).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10-11, 16-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ahmad (US 10,673,439) in view of Noguera Serra (US 2022/0100691).
Regarding claim 1, Ahmad teaches a system on a chip (SoC) (Fig. 1, SoC 100; Col. 4, Lines 49-50, System-on-Chip (SoC) 100), comprising: a hardware accelerator (Figs. 1 and 2, DPE array 102; Col. 28, Lines 22-23, hardware acceleration engines include, but are not limited to, DPEs) comprising data processing engines (DPEs) (Fig. 2, DPEs 204-1 to 204-40) and interface circuitry (Fig. 2, SoC interface block 206), wherein the DPEs are in a first clock domain that uses a first clock (Fig. 2, DPE array 102 with DPEs is in a first clock domain; Col. 8, Lines 5-6, DPE array 102 includes a single clock domain); a second clock domain that uses a second clock with a different frequency than the first clock (Fig. 1, Portions of the SoC are in a second clock domain; Col. 8, Lines 6-8, Other subsystems such as NoC 108, PL 104, PS 106, and the various hardwired circuit blocks 110 may be in one or more separate or different clock domain(s)); and an interface communicatively coupling the hardware accelerator to other circuitry in the SoC (Fig. 1, Network on chip NoC 108 is an interface that couples DPE array 102 (i.e. hardware accelerator) to other circuitry 104/106/110 within SoC 100), wherein the interface circuitry is configured to move data into and out of the hardware accelerator via the interface (Fig. 2, SoC interface block 206 (i.e. interface circuitry) moves data into and out of accelerator 102 via NoC 108 (i.e. the interface) in Figure 1), wherein the interface is communicatively coupled between the DPEs and a memory controller (Fig. 6, Noc 108 (i.e. interface) couples DPE 204 to memory controller within programmable logic (PL) 104; Col. 24, Lines 9-11, DPE array 102 can communicate with each other or other subsystems (e.g., the PS 106 and/or a memory controller) via the NoC 108).
Ahmad does not teach the SoC comprising the hardware accelerator comprising wherein the DPEs are in a first clock domain that uses a first clock and the interface circuitry is in a second clock domain that is separate from the first clock domain and that uses a second clock with a different frequency than the first clock, and wherein the second clock has a higher frequency than the first clock.
Noguera Serra teaches the SoC (Fig. 3, SoC 100) comprising the hardware accelerator (Fig. 3, Die 104 has data processing engine array which is used to accelerate data processing) comprising wherein the DPEs (Figs. 3 and 4, DPE array 110 of Figure 3 comprises DPEs 402 of Figure 4; Paragraph 0056, DPE array 110 is implemented as a plurality of interconnected and programmable DPEs 402) are in a first clock domain that uses a first clock (Fig. 3, DPE array 110 has a first clock frequency; Paragraph 0153, the clock frequency or clock frequencies of DPE array 110 and the generation of reset signals 650 may be set) and the interface circuitry is in a second clock domain that is separate from the first clock domain (Figs. 3 and 4, Physical interface 306 uses a second clock frequency domain separate from the clock frequency of DPEs 402 of DPE array 110; Paragraph 0131, provides an asynchronous clock-domain crossing between DPE array 110 and another clock domain… Paragraph 0164, physical interface 306 and/or other dies coupled thereto operate at a different reference voltage and a different clock speed than DPEs 402) and that uses a second clock with a different frequency than the first clock, wherein the second clock has a higher frequency than the first clock (Figs. 3, 4, and 7, Physical interface 306 can have a higher clock frequency than the DPEs 402; Paragraph 0165, providing an interface that transitions between the clock rate of physical interface 306 or other circuitry and/or other circuitry coupled thereto and the clock rate of DPEs 402… Paragraph 0030, clock signals of different clock domains may have different clock frequencies and/or phases).
Ahmad and Noguera Serra are analogous art because they are in the same field of endeavor of using different power/clock domains within an SoC containing a DPE array coupled to interface circuitry.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ahmad’s SoC to incorporate the teachings of Noguera Serra and include separate clock domains within the single SoC of Ahmad, wherein the interface circuitry of Ahmad can use a second clock frequency that is higher than the first clock frequency of the DPE array of Ahmad.
One of ordinary skill in the art would be motivated to make the modifications in order to provide compatibility between circuitry of varying types, thus providing flexibility to IC designers to implement different generations of circuit technologies and architectures (See Noguera Serra: Paragraph 0028).
Regarding claim 10, Ahmad in view of Noguera Serra teaches the SoC of claim 1. Ahmad teaches the SoC comprising wherein the DPEs are arranged in an array (Fig. 2, DPE array 102), wherein each of the DPEs comprises a core, a memory module, and an interconnect (Fig. 3, DPE 204 includes core 302, memory module 304, and interconnect 306), wherein the interconnects in the DPEs are interconnected so that the DPEs are able to transmit data between each other (Fig. 3, Interconnect 306 connects different DPEs together; Col. 10, Lines 15-17, DPE interconnect 306 facilitates various operations including communication between DPE 204 and one or more other DPEs of DPE array 102).
Regarding claim 11, Ahmad teaches a method, comprising: providing a hardware accelerator (Figs. 1 and 2, DPE array 102; Col. 28, Lines 22-23, hardware acceleration engines include, but are not limited to, DPEs) comprising DPEs (Fig. 2, DPEs 204-1 to 204-40) in a first clock domain (Fig. 2, DPE array 102 with DPEs is in a first clock domain; Col. 8, Lines 5-6, DPE array 102 includes a single clock domain) and interface circuitry (Fig. 2, SoC interface block 206); a second clock domain (Col. 8, Lines 6-8, Other subsystems such as NoC 108, PL 104, PS 106, and the various hardwired circuit blocks 110 may be in one or more separate or different clock domain(s)); operating a first clock in the first clock domain at a first frequency (Fig. 2, First clock domain is at a first frequency); and operating a second clock in the second clock domain at a second frequency different from the first frequency (Col. 8, Lines 6-8, Other subsystems such as NoC 108, PL 104, PS 106, and the various hardwired circuit blocks 110 may be in one or more separate or different clock domain(s)), wherein the interface circuitry is configured to move data into and out of the hardware accelerator via the interface (Fig. 2, SoC interface block 206 (i.e. interface circuitry) moves data into and out of accelerator 102 via NoC 108 (i.e. the interface) in Figure 1), wherein the interface is communicatively coupled between the DPEs and a memory controller (Fig. 6, Noc 108 (i.e. interface) couples DPE 204 to memory controller within programmable logic (PL) 104; Col. 24, Lines 9-11, DPE array 102 can communicate with each other or other subsystems (e.g., the PS 106 and/or a memory controller) via the NoC 108).
Ahmad does not teach the method comprising providing the interface circuitry in a second clock domain that is separate from the first clock domain, and wherein the second clock has a higher frequency than the first clock.
Noguera Serra teaches the method (Fig. 3, SoC 100 operates using a method) comprising providing the interface circuitry in a second clock domain that is separate from the first clock domain (Figs. 3 and 4, Physical interface 306 uses a second clock frequency domain separate from the clock frequency of DPEs 402 of DPE array 110; Paragraph 0131, provides an asynchronous clock-domain crossing between DPE array 110 and another clock domain… Paragraph 0164, physical interface 306 and/or other dies coupled thereto operate at a different reference voltage and a different clock speed than DPEs 402), and wherein the second clock has a higher frequency than the first clock (Figs. 3, 4, and 7, Physical interface 306 can have a higher clock frequency than the DPEs; Paragraph 0165, providing an interface that transitions between the clock rate of physical interface 306 or other circuitry and/or other circuitry coupled thereto and the clock rate of DPEs 402… Paragraph 0030, clock signals of different clock domains may have different clock frequencies and/or phases).
Ahmad and Noguera Serra are analogous art because they are in the same field of endeavor of using different power/clock domains within an SoC containing a DPE array coupled to interface circuitry.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ahmad’s method to incorporate the teachings of Noguera Serra and include separate clock domains within the single SoC of Ahmad, wherein the interface circuitry of Ahmad can use a second clock frequency that is higher than the first clock frequency of the DPE array of Ahmad.
One of ordinary skill in the art would be motivated to make the modifications in order to provide compatibility between circuitry of varying types, thus providing flexibility to IC designers to implement different generations of circuit technologies and architectures (See Noguera Serra: Paragraph 0028).
Regarding claim 16, Ahmad in view of Noguera Serra teaches the method of claim 11. Ahmad teaches the method comprising wherein the hardware accelerator is at least one of an artificial intelligence (AI) accelerator, a cryptography accelerator, or a compression accelerator (Fig. 23, Accelerators include crypto 2036; Col. 3, Lines 58-61, a standard cryptography acceleration function, e.g., Advanced Encryption Standard Galois/Counter mode (AES-GCM), may be implemented using programmable logic).
Regarding claim 17, Ahmad teaches a system, comprising: an IC (Fig. 1, SoC 100; Col. 4, Lines 49-50, System-on-Chip (SoC) 100), comprising: a hardware accelerator (Figs. 1 and 2, DPE array 102; Col. 28, Lines 22-23, hardware acceleration engines include, but are not limited to, DPEs) comprising DPEs in a first clock domain (Fig. 1, DPE are in first clock domain; Col. 8, Lines 5-6, DPE array 102 includes a single clock domain) and interface circuitry (Fig. 2, SoC interface block 206); a second clock domain, wherein, during operation, a first clock in the first clock domain has a different frequency than a second clock in the second clock domain (Col. 8, Lines 6-8, Other subsystems such as NoC 108, PL 104, PS 106, and the various hardwired circuit blocks 110 may be in one or more separate or different clock domain(s)), wherein the interface circuitry is configured to move data into and out of the hardware accelerator via the interface (Fig. 2, SoC interface block 206 (i.e. interface circuitry) moves data into and out of accelerator 102 via NoC 108 (i.e. the interface) in Figure 1), and a memory controller (Figs. 1 and 20, Programmable logic 104 is a memory controller; Col. 28, Lines 36-37, custom memory controllers implemented in the PL regions 104), wherein the interface is communicatively coupled between the DPEs and the memory controller (Fig. 6, Noc 108 (i.e. interface) couples DPE 204 to memory controller within programmable logic (PL) 104; Col. 24, Lines 9-11, DPE array 102 can communicate with each other or other subsystems (e.g., the PS 106 and/or a memory controller) via the NoC 108); and at least one memory coupled to the memory controller in the IC (Figs. 1 and 20, Programmable logic 104 has memory 2054/2056/2058 that is coupled to memory controller in 104; Col. 28, Lines 26-28, “memory resources”, in reference to the SoC 100, includes any memory structures available in the PS 106 and/or the PL regions 104).
Ahmad does not teach the system comprising the hardware accelerator comprising first circuitry in a first clock domain and interface circuitry in a second clock domain that is separate from the first clock domain and wherein, during operation, a first clock in the first clock domain has lower frequency than a second clock in the second clock domain.
Noguera Serra teaches the system (Fig. 3, SoC system 100) comprising the hardware accelerator (Fig. 3, Die 104 has data processing engine array which is used to accelerate data processing) comprising first circuitry in a first clock domain (Fig. 3, DPE array 110 has a first clock frequency; Paragraph 0153, the clock frequency or clock frequencies of DPE array 110 and the generation of reset signals 650 may be set) and interface circuitry in a second clock domain that is separate from the first clock domain (Figs. 3 and 4, Physical interface 306 uses a second clock frequency domain separate from the clock frequency of DPEs 402 of DPE array 110; Paragraph 0131, provides an asynchronous clock-domain crossing between DPE array 110 and another clock domain… Paragraph 0164, physical interface 306 and/or other dies coupled thereto operate at a different reference voltage and a different clock speed than DPEs 402) and wherein, during operation, a first clock in the first clock domain has lower frequency than a second clock in the second clock domain (Figs. 3, 4, and 7, Physical interface 306 can have a higher clock frequency than the DPEs; Paragraph 0165, providing an interface that transitions between the clock rate of physical interface 306 or other circuitry and/or other circuitry coupled thereto and the clock rate of DPEs 402… Paragraph 0030, clock signals of different clock domains may have different clock frequencies and/or phases).
Ahmad and Noguera Serra are analogous art because they are in the same field of endeavor of using different power/clock domains within an SoC containing a DPE array coupled to interface circuitry.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ahmad’s system to incorporate the teachings of Noguera Serra and include separate clock domains within the single SoC of Ahmad, wherein the interface circuitry of Ahmad can use a second clock frequency that is higher than the first clock frequency of the DPE array of Ahmad.
One of ordinary skill in the art would be motivated to make the modifications in order to provide compatibility between circuitry of varying types, thus providing flexibility to IC designers to implement different generations of circuit technologies and architectures (See Noguera Serra: Paragraph 0028).
Regarding claim 20, Ahmad in view of Noguera Serra teaches the system of claim 17. Ahmad teaches the system comprising wherein the first circuitry comprises DPEs arranged in an array (Fig. 2, DPE array 102), wherein each of the DPEs comprises a core, a memory module, and an interconnect (Fig. 3, DPE 204 includes core 302, memory module 304, and interconnect 306), wherein the interconnects in the DPEs are interconnected so that the DPEs are able to transmit data between each other (Fig. 3, Interconnect 306 connects different DPEs together; Col. 10, Lines 15-17, DPE interconnect 306 facilitates various operations including communication between DPE 204 and one or more other DPEs of DPE array 102).
Claims 2-7, 12-15, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ahmad (US 10,673,439) in view of Noguera Serra (US 2022/0100691) and further in view of Pamu (US 2022/0113967).
Regarding claim 2, Ahmad in view of Noguera Serra teaches the SoC of claim 1.
Noguera Serra teaches the SoC comprising wherein the interface circuitry in the second clock domain (Figs. 3 and 4, Physical interface 306 uses a second clock frequency domain separate from the clock frequency of DPEs 402 of DPE array 110; Paragraph 0131, provides an asynchronous clock-domain crossing between DPE array 110 and another clock domain… Paragraph 0164, physical interface 306 and/or other dies coupled thereto operate at a different reference voltage and a different clock speed than DPEs 402), the first clock being a different frequency than the first clock, wherein the second clock has a higher frequency than the first clock (Figs. 3, 4, and 7, Physical interface 306 can have a higher clock frequency than the DPEs; Paragraph 0165, providing an interface that transitions between the clock rate of physical interface 306 or other circuitry and/or other circuitry coupled thereto and the clock rate of DPEs 402… Paragraph 0030, clock signals of different clock domains may have different clock frequencies and/or phases).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ahmad’s SoC to incorporate the teachings of Noguera Serra and include separate clock domains within the single SoC of Ahmad, wherein the interface circuitry of Ahmad can use a second clock frequency that is higher than the first clock frequency of the DPE array of Ahmad.
One of ordinary skill in the art would be motivated to make the modifications in order to provide compatibility between circuitry of varying types, thus providing flexibility to IC designers to implement different generations of circuit technologies and architectures (See Noguera Serra: Paragraph 0028).
Neither Ahmad nor Noguera Serra teaches the SoC comprising wherein the interface circuitry in the second clock domain comprises: an Input-Output Memory Management Unit (IOMMU) comprising circuitry configured to perform a physical to virtual address translation.
Pamu teaches the SoC comprising wherein the interface circuitry in the second clock domain (Fig. 1, Host I/O bridge 119 has a first and second clock domain; Paragraph 0025, bridge 119 may convert clocking of signals between a first clock domain used by the compute request/response handler and/or the memory bridge and a second clock domain) comprises: an Input-Output Memory Management Unit (IOMMU) comprising circuitry configured to perform a physical to virtual address translation (Fig. 1, Host I/O bridge 119 is an IOMMU that performs translation; Paragraph 0033, host I/O bridge 119 may also implement at least a portion of an input-output memory management unit (IOMMU) transaction to translate virtual addresses provided by the compute engine to physical addresses of the system memory 110).
Ahmad, Noguera Serra, and Pamu are analogous art because they are in the same field of endeavor of using different power/clock domains within an SoC.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ahmad/Noguera Serra’s SoC to incorporate the teachings of Pamu and include an IOMMU within the interface circuitry.
One of ordinary skill in the art would be motivated to make the modifications in order to provide security between different circuitry of the SoC while also providing abstraction between the different circuitry which use different addressing schemes (See Pamu: Paragraph 0034).
Regarding claim 3, the combination of Ahmad/Noguera Serra/Pamu teaches the SoC of claim 2. Ahmad teaches the SoC comprising wherein the other circuitry comprises at least one central processing unit (CPU) (Fig. 1, Processor system 106 is a CPU).
Pamu teaches the SoC comprising wherein the IOMMU is configured to translate virtual addresses used by the hardware accelerator to physical addresses used by the at least one CPU before transmitting data from the hardware accelerator to the interface (Fig. 1, Host I/O bridge 119 (i.e. IOMMU) translates between compute engine 112 (i.e. hardware accelerator) and host processing unit 106 (i.e. CPU) connected to system memory 110 via virtual to physical addresses via interface 126 (i.e. the interface); Paragraph 0033, host I/O bridge 119 may also implement at least a portion of an input-output memory management unit (IOMMU) transaction to translate virtual addresses provided by the compute engine to physical addresses of the system memory 110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ahmad/Noguera Serra’s SoC to incorporate the teachings of Pamu and include an IOMMU within the interface circuitry.
One of ordinary skill in the art would be motivated to make the modifications in order to provide security between different circuitry of the SoC while also providing abstraction between the different circuitry which use different addressing schemes (See Pamu: Paragraph 0034).
Regarding claim 4, the combination of Ahmad/Noguera Serra/Pamu teaches the SoC of claim 3. Ahmad teaches the SoC comprising wherein the CPU is in a different clock domain than the first clock domain (Fig. 1, DPE array 102 and CPU 106 have different clock domains; Col. 8, Lines 5-8, DPE array 102 includes a single clock domain. Other subsystems such as NoC 108, PL 104, PS 106, and the various hardwired circuit blocks 110 may be in one or more separate or different clock domain(s)).
Regarding claim 5, the combination of Ahmad/Noguerra Serra/Pamu teaches the SoC of claim 4. Ahmad teaches the SoC comprising wherein the CPU is in a third clock domain that is separate from the first and second clock domains (Fig. 1, DPE array 102 and CPU 106 can have any number of different clock domains; Col. 8, Lines 5-8, DPE array 102 includes a single clock domain. Other subsystems such as NoC 108, PL 104, PS 106, and the various hardwired circuit blocks 110 may be in one or more separate or different clock domain(s)).
Regarding claim 6, the combination of Ahmad/Noguera Serra/Pamu teaches the SoC of claim 2. Ahmad teaches the SoC comprising wherein the interface circuitry further comprises a network on chip (NoC) (Fig. 5, Tiles 502-520 are part of interface block 206 and is a network on a chip), wherein the interface circuitry communicate with the DPEs through the NoC (Fig. 5, Tiles are used to communicate with DPEs; Col. 16, Lines 50-51, tiles 502-520 are coupled so that data may be propagated from one tile to another).
Noguera Serra teaches the SoC comprising wherein the interface circuitry further comprises a controller (Fig. 11, Controller 1002-1 of physical interface 306 controls addressing and clocking/power management; Paragraph 0186, Circuit block 1002-1 includes a data channel circuit 1102, a command address circuit 1104, and a clock and power manager 1106) and a network on chip (NoC) (Fig. 6A, Tiles 408 are coupled to physical interface 306), wherein the controller and the interface circuitry communicate with the DPEs through the NoC (Fig. 13, Physical interface 306-1 communicates via controller and through the NoC tiles 408; Paragraph 0184, any data streams received from an interface of tile 408 (e.g., bitwise interface 610, DMA engine 612, and/or stream interface 614) may be provided to different circuit blocks 1002).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ahmad/Noguera Serra/Pamu’s SoC to incorporate further teachings of Noguera Serra and include address/clocking/power control in the interface circuitry of Ahmad.
One of ordinary skill in the art would be motivated to make the modifications in order to provide compatibility between circuitry of varying types, thus providing flexibility to IC designers to implement different generations of circuit technologies and architectures (See Noguera Serra: Paragraph 0028).
Pamu teaches the SoC comprising the interface circuitry is an IOMMU (Fig. 1, Host I/O bridge 119 is an IOMMU that performs translation; Paragraph 0033, host I/O bridge 119 may also implement at least a portion of an input-output memory management unit (IOMMU) transaction to translate virtual addresses provided by the compute engine to physical addresses of the system memory 110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ahmad/Noguera Serra’s SoC to incorporate the teachings of Pamu and include an IOMMU within the interface circuitry.
One of ordinary skill in the art would be motivated to make the modifications in order to provide security between different circuitry of the SoC while also providing abstraction between the different circuitry which use different addressing schemes (See Pamu: Paragraph 0034).
Regarding claim 7, the combination of Ahmad/Noguera Serra/Pamu teaches the SoC of claim 6. Ahmad teaches the SoC comprising wherein the controller communicates with a CPU only through the interface, wherein the interface is a second NoC (Fig. 1, NoC 108 is the second NoC and is the only way to communicate between the interface in DPE array 102 and the CPU 106).
Noguera Serra teaches the SoC comprising wherein the second NoC is larger than the NoC in the hardware accelerator (Fig. 3, NoC of physical interface 306 can be of different sizes; Paragraph 0052, FIGS. 1 and/or 2, may be implemented so that dies 104, 106, interposer 102, and/or bridge die 202 are implemented using different process technologies (e.g., with different features sizes)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ahmad/Noguera Serra/Pamu’s SoC to incorporate further teachings of Noguera Serra and enable the second NoC to be larger than the first NoC.
One of ordinary skill in the art would be motivated to make the modifications in order to provide compatibility between circuitry of varying types, thus providing flexibility to IC designers to implement different generations of circuit technologies and architectures (See Noguera Serra: Paragraph 0028).
Regarding claim 12, Ahmad in view of Noguera Serra teaches the method of claim 11.
Noguera Serra teaches the method comprising wherein the interface circuitry in the second clock domain (Figs. 3 and 4, Physical interface 306 uses a second clock frequency domain separate from the clock frequency of DPEs 402 of DPE array 110; Paragraph 0131, provides an asynchronous clock-domain crossing between DPE array 110 and another clock domain… Paragraph 0164, physical interface 306 and/or other dies coupled thereto operate at a different reference voltage and a different clock speed than DPEs 402).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ahmad’s method to incorporate the teachings of Noguera Serra and include separate clock domains within the single SoC of Ahmad, wherein the interface circuitry of Ahmad can use a second clock frequency that is higher than the first clock frequency of the DPE array of Ahmad.
One of ordinary skill in the art would be motivated to make the modifications in order to provide compatibility between circuitry of varying types, thus providing flexibility to IC designers to implement different generations of circuit technologies and architectures (See Noguera Serra: Paragraph 0028).
Neither Ahmad nor Noguera Serra teaches the method comprising wherein the interface circuitry in the second clock domain comprises: an IOMMU comprising circuitry configured to perform a physical to virtual address translation.
Pamu teaches the method comprising wherein the interface circuitry in the second clock domain (Fig. 1, Host I/O bridge 119 has a first and second clock domain; Paragraph 0025, bridge 119 may convert clocking of signals between a first clock domain used by the compute request/response handler and/or the memory bridge and a second clock domain) comprises: an IOMMU comprising circuitry configured to perform a physical to virtual address translation (Fig. 1, Host I/O bridge 119 is an IOMMU that performs translation; Paragraph 0033, host I/O bridge 119 may also implement at least a portion of an input-output memory management unit (IOMMU) transaction to translate virtual addresses provided by the compute engine to physical addresses of the system memory 110).
Ahmad, Noguera Serra, and Pamu are analogous art because they are in the same field of endeavor of using different power/clock domains within an SoC.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ahmad/Noguera Serra’s method to incorporate the teachings of Pamu and include an IOMMU within the interface circuitry.
One of ordinary skill in the art would be motivated to make the modifications in order to provide security between different circuitry of the SoC while also providing abstraction between the different circuitry which use different addressing schemes (See Pamu: Paragraph 0034).
Regarding claim 13, the combination of Ahmad/Noguera Serra/Pamu teaches the method of claim 12. Ahmad teaches the method comprising a central processing unit (CPU) (Fig. 1, Processor system 106 is a CPU).
Pamu teaches the method further comprising: translating, using the IOMMU, virtual addresses used by the hardware accelerator to physical addresses used by a CPU before transmitting data from the hardware accelerator to the CPU, wherein the CPU is in a same SoC as the hardware accelerator (Fig. 1, Host I/O bridge 119 (i.e. IOMMU) translates between compute engine 112 (i.e. hardware accelerator) and host processing unit 106 (i.e. CPU) connected to system memory 110 via virtual to physical addresses via interface 126 (i.e. the interface); Paragraph 0033, host I/O bridge 119 may also implement at least a portion of an input-output memory management unit (IOMMU) transaction to translate virtual addresses provided by the compute engine to physical addresses of the system memory 110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ahmad/Noguera Serra’s method to incorporate the teachings of Pamu and include an IOMMU within the interface circuitry.
One of ordinary skill in the art would be motivated to make the modifications in order to provide security between different circuitry of the SoC while also providing abstraction between the different circuitry which use different addressing schemes (See Pamu: Paragraph 0034).
Regarding claim 14, the combination of Ahmad/Noguera Serra/Pamu teaches the method of claim 13. Ahmad teaches the method comprising wherein the CPU is in a different clock domain than the first clock domain (Fig. 1, DPE array 102 and CPU 106 have different clock domains; Col. 8, Lines 5-8, DPE array 102 includes a single clock domain. Other subsystems such as NoC 108, PL 104, PS 106, and the various hardwired circuit blocks 110 may be in one or more separate or different clock domain(s)).
Regarding claim 15, the combination of Ahmad/Noguera Serra/Pamu teaches the method of claim 14. Ahmad teaches the method comprising wherein the CPU is in a third clock domain that is separate from the first and second clock domains (Fig. 1, DPE array 102 and CPU 106 can have any number of different clock domains; Col. 8, Lines 5-8, DPE array 102 includes a single clock domain. Other subsystems such as NoC 108, PL 104, PS 106, and the various hardwired circuit blocks 110 may be in one or more separate or different clock domain(s)).
Regarding claim 18, Ahmad in view of Noguera Serra teaches the system of claim 17.
Noguera Serra teaches the system comprising wherein the interface circuitry in the second clock domain (Figs. 3 and 4, Physical interface 306 uses a second clock frequency domain separate from the clock frequency of DPEs 402 of DPE array 110; Paragraph 0131, provides an asynchronous clock-domain crossing between DPE array 110 and another clock domain… Paragraph 0164, physical interface 306 and/or other dies coupled thereto operate at a different reference voltage and a different clock speed than DPEs 402).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ahmad’s system to incorporate the teachings of Noguera Serra and include separate clock domains within the single SoC of Ahmad, wherein the interface circuitry of Ahmad can use a second clock frequency that is higher than the first clock frequency of the DPE array of Ahmad.
One of ordinary skill in the art would be motivated to make the modifications in order to provide compatibility between circuitry of varying types, thus providing flexibility to IC designers to implement different generations of circuit technologies and architectures (See Noguera Serra: Paragraph 0028).
Neither Ahmad nor Noguera Serra teaches the system comprising wherein the interface circuitry in the second clock domain comprises: an IOMMU comprising circuitry configured to perform a physical to virtual address translation.
Pamu teaches the SoC comprising he system comprising wherein the interface circuitry in the second clock domain (Fig. 1, Host I/O bridge 119 has a first and second clock domain; Paragraph 0025, bridge 119 may convert clocking of signals between a first clock domain used by the compute request/response handler and/or the memory bridge and a second clock domain) comprises: an IOMMU comprising circuitry configured to perform a physical to virtual address translation (Fig. 1, Host I/O bridge 119 is an IOMMU that performs translation; Paragraph 0033, host I/O bridge 119 may also implement at least a portion of an input-output memory management unit (IOMMU) transaction to translate virtual addresses provided by the compute engine to physical addresses of the system memory 110).
Ahmad, Noguera Serra, and Pamu are analogous art because they are in the same field of endeavor of using different power/clock domains within an SoC.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ahmad/Noguera Serra’s system to incorporate the teachings of Pamu and include an IOMMU within the interface circuitry.
One of ordinary skill in the art would be motivated to make the modifications in order to provide security between different circuitry of the SoC while also providing abstraction between the different circuitry which use different addressing schemes (See Pamu: Paragraph 0034).
Regarding claim 19, the combination of Ahmad/Noguera Serra/Pamu teaches the system of claim 18. Ahmad teaches the system comprising wherein the IC comprises a central processing unit (CPU) (Fig. 1, Processor system 106 is a CPU).
Pamu teaches the system comprising wherein the IC comprises an interconnect, wherein the interconnect couples the CPU to a controller in the hardware accelerator and the IOMMU in the hardware accelerator (Fig. 1, Interconnect 126 couples CPU 106 to accelerator 102 and IOMMU 119 within accelerator 102; Paragraph 0033, host I/O bridge 119 may also implement at least a portion of an input-output memory management unit (IOMMU) transaction to translate virtual addresses provided by the compute engine to physical addresses of the system memory 110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ahmad/Noguera Serra’s system to incorporate the teachings of Pamu and include an IOMMU within the interface circuitry.
One of ordinary skill in the art would be motivated to make the modifications in order to provide security between different circuitry of the SoC while also providing abstraction between the different circuitry which use different addressing schemes (See Pamu: Paragraph 0034).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ahmad (US 10,673,439) in view of Noguera Serra (US 2022/0100691) and further in view of Nampoothiri (US 2018/0267595).
Regarding claim 9, Ahmad in view of Noguera Serra teaches the SoC of claim 1. Neither Ahmad nor Noguera Serra teaches the SoC comprising wherein the SoC is configured to increase and decrease a frequency of the second clock in response to data movement demand thresholds corresponding to the interface circuitry.
Nampoothiri teaches the SoC (Fig. 1, SoC 100; Paragraph 0028, FIG. 1 illustrates example components and interconnections in a system-on-chip (SoC) 100) comprising wherein the SoC is configured to increase and decrease a frequency of the second clock in response to data movement demand thresholds (Fig. 2, Calculate demand thresholds in step 204 and increase/decrease clock frequency in step 206; Paragraph 0039, At 204, the CRM calculates an adjusted bandwidth for operating the memory based on the determined efficiency. At 206, the CRM adjusts at least one of a voltage or a clock frequency of the memory interface/bus to the memory based on the determined adjusted bandwidth) corresponding to the interface circuitry (Fig. 1, Memory interface/bus 126 changes clock frequency; Paragraph 0035, SoC typically adds up the bandwidth votes from multiple IP cores and then computes a minimum frequency to operate the memory interface/bus 126 needed for the bandwidth votes (referred to herein as DDR_BW_freq)).
Ahmad, Noguera Serra, and Nampoothiri are analogous art because they are in the same field of endeavor of using different power/clock domains within an SoC.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ahmad/Noguera Serra’s SoC to incorporate the teachings of Nampoothiri and enable the frequency of the interface circuitry to be increased or decreased based on demand thresholds.
One of ordinary skill in the art would be motivated to make the modifications in order to reduce power consumption in SoC devices by dynamically accounting for memory efficiency and keeping bus clocks at optimum levels to meet a desired performance level (See Nampoothiri: Paragraph 0026).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PGPUB 2022/0294455 to Kumashikar discloses that different IC components can use different clock frequencies based on detected thermal and power thresholds (See Paragraph 0019).
US PGPUB 2015/0162311 to Bartley discloses that a variety of factors influencing chip design include heat output, power demands, communication bandwidth between cores and data bus and I/O devices, wherein a clock frequency can be adjusted based on these factors (See Paragraph 0086).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY Z WANG whose telephone number is (571)270-1716. The examiner can normally be reached 9 am - 3 pm (Monday-Friday).
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/H.Z.W./Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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