Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. Pub. No. 20170294479 to Cha et al. (Cha).
Regarding Claim 1, Huang teaches in Fig. 3A at least, monolithic array chip, including:
a first semiconductor layer 101P;
a common electrode 143c located on the first semiconductor layer;
a first light-emitting unit 151 with a first electrode located on the first semiconductor layer;
a second light-emitting unit 152 with a second electrode located on the first semiconductor layer; and
a third light-emitting unit 153 with a third electrode (134 on each) located on the first semiconductor layer,
wherein the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are separated from each other by a trench (not numbered, see Fig. 3A for example).
Claims 1, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. Pub. No. 20220059606 to Huang et al. (Huang).
Regarding Claim 1, Huang teaches in Fig. 9C at least, monolithic array chip, including:
a first semiconductor layer 12;
a common electrode 30 located on the first semiconductor layer;
a first light-emitting unit with a first electrode located on the first semiconductor layer;
a second light-emitting unit with a second electrode located on the first semiconductor layer; and
a third light-emitting unit with a third electrode located on the first semiconductor layer (three of 11/14/20),
wherein the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are separated from each other by a trench (between layers 11).
Regarding Claim 3, Huang teaches the monolithic array chip according to claim 1, wherein the first light- emitting unit, the second light-emitting unit and the third light-emitting unit emit the same peak wavelength ([0050]; LEDs emit same color which are converted to RGB by QD wavelength converters).
Regarding Claim 4, Huang teaches the monolithic array chip according to claim 3, further including a first wavelength conversion layer 50R located on the first light-emitting unit, the first wavelength conversion layer absorbing the peak wavelength to emit a first converted wavelength different from the peak wavelength (see Fig. 8B for example).
Regarding Claim 5, Huang teaches the monolithic array chip according to claim 3, further including a second wavelength conversion layer 50G located on the second light-emitting unit, the second wavelength conversion layer absorbs the peak wavelength to emit a second converted wavelength different from the peak wavelength.
Regarding Claim 6, Huang teaches the monolithic array chip according to claim 1, wherein the monolithic array chip includes a first light-emitting area capable of emitting the red light located on the first light-emitting unit, a second light-emitting area capable of emitting the green light located on the second light-emitting unit, and a third light-emitting area capable of emitting the blue light located on the third light-emitting unit (see Fig 8B).
Regarding Claim 10, Huang teaches the monolithic array chip according to claim 1, wherein the common electrode is spaced apart from one of the first electrode, the second electrode and the third electrode by a spacing, and the space is less than or equal to 1/2 or 1/3 of a length of a side of the monolithic array chip (see Fig. 9C, common anode 30 is spaced opposite from each of electrodes 20 on each LED).
Regarding Claim 17, Huang teaches the monolithic array chip according to claim 14, wherein the second light-emitting unit and the common electrode are located on a diagonal line on the monolithic array chip (see Fig. 9A; one of 3 LEDs are diagonal to common anode 30).
Regarding Claim 18, Huang teaches the monolithic array chip according to claim 1, wherein any two light- emitting units of the first light-emitting unit, the second light-emitting unit and the third light-emitting unit are located on a diagonal line on the monolithic array chip, and each of the any two light-emitting units includes one side parallel to each other (see Fig. 9C).
Regarding Claim 19, Huang teaches the monolithic array chip according to claim 18, wherein there is a distance between the sides of the any two light-emitting units that is greater than the minimum width of the trench (see Fig. 9C; distance between layers 14 is greater than the trench between layers 11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2- are rejected under 35 U.S.C. 103 as being unpatentable over Huang.
Regarding Claim 2, Huang teaches the monolithic array chip according to claim 1, but does not explicitly teach that the trench includes a minimum width less than or equal to 3 um. However, the distance between the LEDs directly affects the density and therefore the intensity of light generated, and is therefore a result effective variable that may be optimized by the person of ordinary skill to meet application specific requirements (MPEP 2144.05(II)(B)).
Regarding Claims 7 and 8, Huang teaches the monolithic array chip according to claim 1, but does not explicitly teach that the monolithic array chip includes a side having a length not greater than 90 um, 75 um, 60 um, 50 um, 40 um or not more than 30 um, or that the first light- emitting unit, the second light-emitting unit, and the third light-emitting unit each includes an area not larger than 4900 um2, 3600 um2, 2500 um2, 1600 um2, 900 um2, 400 um2, or 100 um2.. However, length of the LEDs, and therefore the area, directly affects the intensity of light generated, and is therefore a result effective variable that may be optimized by the person of ordinary skill to meet application specific requirements (MPEP 2144.05(II)(B)).
Regarding Claim 9, Huang teaches the monolithic array chip according to claim 1, but does not explicitly teach that the common electrode, the first electrode, the second electrode, and the third electrode each includes an area less than 10 um2. However, the surface area of the electrodes directly affects the current carrying capability of the electrode, and is therefore a result effective variable that may be optimized by the person of ordinary skill to meet application specific requirements (MPEP 2144.05(II)(B)).
Regarding Claim 20, Huang a teaches light-emitting module including:
a circuit board (display taught throughout; a circuit board is implicit and/or inherent to a display device); and
a plurality of monolithic array chips (would be required to form a display) according to any one of claim 4 to claim 20 are located on the circuit board, but does not explicitly teach that the plurality of monolithic array chips are separated from each other by a separation lane including a width less than 1000 um. However, see above regarding optimization of density.
Claims 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Cha in view of U.S. Pat. Pub. No. 20180277592 to Moon et al. (Moon).
Regarding Claims 11 and 13, Cha teaches the monolithic array chip according to claim 1, but does not explicitly teach that the first light- emitting unit, the second light-emitting unit, and the third light-emitting unit include different top view areas or that each of the first light-emitting unit and the third light-emitting unit includes a top view area that is larger than the top view area of the second light-emitting unit.
However, in analogous art, Moon teaches monolithically integrated LEDs my have different areas to compensate for the difference in emission efficiency; a less efficiently emitting LED will have to be larger than the others. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Moon and modify Cha with variously sized LEDs to compensate for efficiency differences, as taught by Moon [0055,0066].
Conclusion
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/EVREN SEVEN/Primary Examiner, Art Unit 2812
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