DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 12-20 in the reply filed on 7/13/26 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 12-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lanka et al. (US pub 20210225827).
With respect to claim 12, Lanka et al. teach a memory package comprising (see figs. 1-11, particularly fig. 1A-1B and associated text):
a first memory physical layer (PHY) interface (right HBM, third HBM from top) positioned on a surface of a compute die (right HBM, 4th HBM from top);
a first memory (right HBM, second HBM from top) connected to the first memory PHY interface of the compute die via a first through-silicon via (TSV) connection (connectors through the HBM);
a base die (left HBM, 4th HBM from top) coupled with the compute die and positioned on a silicon interposer (interposer, see para 0044), wherein the compute die is positioned on the silicon interposer and connected to the base die via the silicon interposer; and
a second memory (left HBM, third from top) connected to the base die.
With respect to claim 13, Lanka et al. teach the first memory comprises a first memory die (right HBM, third HBM from top) stacked on the first memory PHY interface and a second memory die (right HBM, top HBM) stacked on the first memory die. See figs. 1A-1B and associated text.
With respect to claim 14, Lanka et al. teach the first memory die connects to the first memory PHY interface via the first TSV connection, and the second memory die connects to the first memory die via the first TSV connection. See figs. 1A-1B and associated text.
With respect to claim 15, Lanka et al. teach the second memory comprises a third memory die (left HBM, third from top) stacked on the base die and a fourth memory die (left HBM, second from top) stacked on the third memory die. See figs. 1A-1B and associated text.
With respect to claim 16, Lanka et al. teach the third memory die connects to the base die via a second TSV connection (vias from left HBM), and the fourth memory die connect to the third memory die via the second TSV connection. See figs. 1A-1B and associated text.
Claim(s) 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lanka et al. (US pub 20210225827).
With respect to claim 18, Lanka et al. teach a system on chip (SoC) comprising (see figs. 1-11, particularly fig. 1A-1B and associated text):
a compute die (right HBM, 4th HBM from top) positioned on a silicon interposer (interposer, see para 0044);
a base die (left HBM, 4th HBM from top) coupled with the compute die and positioned on the silicon interposer; and
a memory coupled with the compute die and the base die, the memory comprising:
a first memory physical layer (PHY) interface (right HBM, third HBM from top) positioned on a surface of the compute die;
a first memory (right HBM, second HBM from top) connected to the first memory PHY interface of the compute die via a first through-silicon via (TSV) connection (connectors through the HBM); and
a second memory (left HBM, third from top) connected to the base die via a second TSV connection.
With respect to claim 19, Lanka et al. teach the first memory comprises a first memory die (right HBM, third HBM from top) stacked on the first memory PHY interface and a second memory die (right HBM, top HBM) stacked on the first memory die. See figs. 1A-1B and associated text.
With respect to claim 20, Lanka et al. teach the first memory die connects to the first memory PHY interface via the first TSV connection, and the second memory die connects to the first memory die via the first TSV connection. See figs. 1A-1B and associated text.
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Examiner’s Cited References
The cited references generally show the similar or related structure having a first memory stack and a second memory stack over an interposer and connected via the interposer, where a bottom die of the second memory stack having a memory layer connected to a top die, where a bottom die of the first memory stack connected to a top die as presently claimed by applicant.
Conclusion
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LONG . PHAM
Examiner
Art Unit 2823
/LONG PHAM/Primary Examiner, Art Unit 2897
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